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    AUXILIARY COLORING METHOD FOR APERIODIC PATTERN QUAD-COLOR SPLIT
    2.
    发明公开
    AUXILIARY COLORING METHOD FOR APERIODIC PATTERN QUAD-COLOR SPLIT 审中-公开

    公开(公告)号：US20240346216A1

    公开(公告)日：2024-10-17

    申请号：US18426033

    申请日：2024-01-29

    申请人： Shanghai Huali Integrated Circuit Corporation

    发明人： Baoxuan LI

    IPC分类号： G06F30/30

    CPC分类号： G06F30/30

    摘要： The present application provides an auxiliary coloring method for an aperiodic pattern quad-color split, including: analyzing a split rule and a pattern design rule according to a lithography capability; finding a general solution of the split rule that satisfies the lithography capability, wherein the general solution covers a pattern distribution allowed by the pattern design rule; extracting a partial rule from the general solution, and pre-coloring patterns; and writing a script to split remaining uncolored patterns using software. According to the present application, by analyzing the rules, the amount of computer computation can be reduced greatly, thereby limiting the problem within the reach of the computer computation capability and obtaining a correct split solution within short running time.

    Variant model-based compilation for analog simulation
    8.
    发明授权
    Variant model-based compilation for analog simulation 有权

    公开(公告)号：US12001771B2

    公开(公告)日：2024-06-04

    申请号：US17412404

    申请日：2021-08-26

    申请人： Siemens Industry Software Inc.

    发明人： Peter Foelsche

    IPC分类号： G06F30/30 ,  G06F30/323 ,  G06F30/367

    CPC分类号： G06F30/367 ,  G06F30/323

    摘要： A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and branches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.

    Systems and methods for co-simulation
    10.
    发明授权
    Systems and methods for co-simulation 有权

    公开(公告)号：US11966675B2

    公开(公告)日：2024-04-23

    申请号：US17529742

    申请日：2021-11-18

    申请人： The MathWorks, Inc.

    发明人： Tao Cheng ,  Pieter J. Mosterman ,  Haihua Feng ,  Fu Zhang

    IPC分类号： G06F11/07 ,  G06F30/20 ,  G06F30/30

    CPC分类号： G06F30/30 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F30/20

    摘要： A model including a first co-simulation component and a second co-simulation component is analyzed. During execution of the model, the first co-simulation component outputs data to the second co-simulation component via a connection. The connection is declared as a continuous-time rate connection for input of the data into the second co-simulation component. Based on analyzing the model, the connection is identified as a discrete-continuous sample time connection based on data being communicated from the first co-simulation component to the second co-simulation component via the connection at a discrete-time rate when the model is executed in a co-simulation manner.