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22 条记录 (耗时 0.015 秒)

    Mask rule checking for curvilinear masks for electronic circuits
    1.
    发明授权
    Mask rule checking for curvilinear masks for electronic circuits 有权

    公开(公告)号：US11222160B2

    公开(公告)日：2022-01-11

    申请号：US16892252

    申请日：2020-06-03

    申请人： Synopsys, Inc.

    发明人： Thomas Christopher Cecil

    IPC分类号： G06F30/398 ,  G03F1/36

    摘要： A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.

    Sub-resolution assist feature implementation with shot optimization
    2.
    发明授权
    Sub-resolution assist feature implementation with shot optimization 有权
    子分辨率辅助功能实现与镜头优化

    公开(公告)号：US09471746B2

    公开(公告)日：2016-10-18

    申请号：US14922569

    申请日：2015-10-26

    申请人： Synopsys, Inc.

    发明人： Michael Lawrence Rieger ,  Thomas Christopher Cecil ,  Benjamin David Painter

    IPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70

    CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5072

    摘要： A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

    摘要翻译： 半导体芯片的设计布局包括关于要制造的形状的信息。 产生光刻曝光“镜头”的集群并且经受射出密度的测量以接近在晶片制造期间暴露时产生期望的制造形状的掩模形状。 在镜头集群上运行模拟，以估计所创建的集群的结果制造形状。 修改照片群以将估计的制造形状与期望的制造形状更紧密地对准。 模拟和修改镜头的过程是迭代的，重复，直到估计的制造形状在计划的制造形状的期望误差之内。

    Enforcing mask synthesis consistency across random areas of integrated circuit chips
    3.
    发明申请
    Enforcing mask synthesis consistency across random areas of integrated circuit chips 有权

    公开(公告)号：US20220276554A1

    公开(公告)日：2022-09-01

    申请号：US17749952

    申请日：2022-05-20

    申请人： Synopsys, Inc.

    发明人： Thomas Christopher Cecil ,  Kevin Hooker

    IPC分类号： G03F1/70 ,  G06F16/51 ,  G06F30/392 ,  G03F1/36 ,  G03F1/44

    摘要： A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

    Sub-resolution assist feature implementation using shot optimization
    4.
    发明授权
    Sub-resolution assist feature implementation using shot optimization 有权
    使用镜头优化的子分辨率辅助功能实现

    公开(公告)号：US09170481B2

    公开(公告)日：2015-10-27

    申请号：US14213813

    申请日：2014-03-14

    申请人： Synopsys, Inc.

    发明人： Michael Lawrence Rieger ,  Thomas Christopher Cecil ,  Benjamin David Painter

    IPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70

    CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5072

    摘要： A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

    摘要翻译： 半导体芯片的设计布局包括关于要制造的形状的信息。 产生光刻曝光“镜头”的集群并且经受射出密度的测量以接近在晶片制造期间暴露时产生期望的制造形状的掩模形状。 在镜头集群上运行模拟，以估计所创建的集群的结果制造形状。 修改照片群以将估计的制造形状与期望的制造形状更紧密地对准。 模拟和修改镜头的过程是迭代的，重复，直到估计的制造形状在计划的制造形状的期望误差之内。

    SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION
    5.
    发明申请
    SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION 有权
    分解协助使用优化优化实现特征

    公开(公告)号：US20140282290A1

    公开(公告)日：2014-09-18

    申请号：US14213813

    申请日：2014-03-14

    申请人： Synopsys, Inc.

    发明人： Michael Lawrence Rieger ,  Thomas Christopher Cecil ,  Benjamin David Painter

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5072

    摘要： A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

    摘要翻译： 半导体芯片的设计布局包括关于要制造的形状的信息。 产生光刻曝光“镜头”的集群并且经受射出密度的测量以接近在晶片制造期间暴露时产生期望的制造形状的掩模形状。 在镜头集群上运行模拟，以估计所创建的集群的结果制造形状。 修改照片群以将估计的制造形状与期望的制造形状更紧密地对准。 模拟和修改镜头的过程是迭代的，重复，直到估计的制造形状在计划的制造形状的期望误差之内。

    Classification of patterns in an electronic circuit layout using machine learning based encoding
    7.
    发明授权
    Classification of patterns in an electronic circuit layout using machine learning based encoding 有权

    公开(公告)号：US11663485B2

    公开(公告)日：2023-05-30

    申请号：US16876382

    申请日：2020-05-18

    申请人： Synopsys, Inc.

    发明人： Thomas Christopher Cecil

    IPC分类号： G06N3/08 ,  G06N3/084

    CPC分类号： G06N3/084

    摘要： A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The clusters of circuit patterns may be used for training and evaluation of machine learning based models.

    CLASSIFICATION OF PATTERNS IN AN ELECTRONIC CIRCUIT LAYOUT USING MACHINE LEARNING BASED ENCODING
    8.
    发明申请
    CLASSIFICATION OF PATTERNS IN AN ELECTRONIC CIRCUIT LAYOUT USING MACHINE LEARNING BASED ENCODING 审中-公开

    公开(公告)号：US20200372365A1

    公开(公告)日：2020-11-26

    申请号：US16876382

    申请日：2020-05-18

    申请人： Synopsys, Inc.

    发明人： Thomas Christopher Cecil

    IPC分类号： G06N3/08

    摘要： A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The clusters of circuit patterns may be used for training and evaluation of machine learning based models.

    Sub-resolution assist feature implementation for shot generation
    9.
    发明授权
    Sub-resolution assist feature implementation for shot generation 有权

    公开(公告)号：US10318697B2

    公开(公告)日：2019-06-11

    申请号：US15289919

    申请日：2016-10-10

    申请人： Synopsys, Inc.

    发明人： Michael Lawrence Rieger ,  Thomas Christopher Cecil ,  Benjamin David Painter

    IPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70

    摘要： A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.