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    STANDARD CELL DESIGN
    1.
    发明公开
    STANDARD CELL DESIGN 审中-公开

    公开(公告)号：US20240362392A1

    公开(公告)日：2024-10-31

    申请号：US18769843

    申请日：2024-07-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F111/20

    CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

    Systems and methods for integrated circuit layout
    2.
    发明授权
    Systems and methods for integrated circuit layout 有权

    公开(公告)号：US12131108B2

    公开(公告)日：2024-10-29

    申请号：US18518167

    申请日：2023-11-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kenan Yu ,  Qingwen Deng

    IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

    CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/20

    Abstract: A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

    METHOD AND DEVICE FOR DETERMINING DIVIDING POSITION AND INTEGRATION OF AUTOMOTIVE PART
    5.
    发明公开
    METHOD AND DEVICE FOR DETERMINING DIVIDING POSITION AND INTEGRATION OF AUTOMOTIVE PART 审中-公开

    公开(公告)号：US20240320389A1

    公开(公告)日：2024-09-26

    申请号：US18271741

    申请日：2021-10-01

    Applicant: JFE STEEL CORPORATION

    Inventor： Takanobu SAITO

    IPC: G06F30/20 ,  G06F30/15 ,  G06F111/04 ,  G06F111/06 ,  G06F111/20

    CPC classification number: G06F30/20 ,  G06F30/15 ,  G06F2111/04 ,  G06F2111/06 ,  G06F2111/20

    Abstract: A dividing position and integration of automotive parts determination method includes: acquiring an automotive body model including automotive parts modeled by elements and joining points at which the automotive parts are joined as a parts assembly; setting objectives related to automotive body performance of the automotive body model, constraints related to a volume of the automotive body model, and load and constraint condition or only loading condition given to the automotive body model, and obtaining sensitivity of each of the elements in each of the automotive parts satisfying the objectives under the load and constraint condition or only the loading condition and the constraints; and determining a position where the automotive part is divided and/or the automotive parts to be integrated based on the sensitivity of each of the elements in each of the automotive part.

    Method of manufacturing semiconductor device and system for same
    6.
    发明授权
    Method of manufacturing semiconductor device and system for same 有权

    公开(公告)号：US12093629B2

    公开(公告)日：2024-09-17

    申请号：US18335505

    申请日：2023-06-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ke-Ying Su ,  Ze-Ming Wu ,  Po-Jui Lin

    IPC: G06F30/392 ,  G06F30/398 ,  G06F111/20 ,  G06F119/18

    CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20 ,  G06F2119/18

    Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.

    Standard cell design
    10.
    发明授权
    Standard cell design 有权

    公开(公告)号：US12073165B2

    公开(公告)日：2024-08-27

    申请号：US17476615

    申请日：2021-09-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC: G06F30/30 ,  G06F30/323 ,  G06F30/392 ,  G06F30/398 ,  G06F111/20

    CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

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