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    Integrated circuit, system for and method of forming an integrated circuit
    6.
    发明授权
    Integrated circuit, system for and method of forming an integrated circuit 有权

    公开(公告)号：US10797041B2

    公开(公告)日：2020-10-06

    申请号：US16205014

    申请日：2018-11-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Po-Hsiang Huang ,  Lipen Yuan

    IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

    Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.

    Integrated circuit structure
    7.
    发明授权
    Integrated circuit structure 有权

    公开(公告)号：US10776557B2

    公开(公告)日：2020-09-15

    申请号：US16205039

    申请日：2018-11-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Po-Hsiang Huang ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang

    IPC: G06F30/398 ,  H01L27/02 ,  G03F1/36 ,  H01L27/118 ,  G06F30/392 ,  G06F30/394 ,  G06F111/04 ,  G06F119/18

    Abstract: A semiconductor structure includes first and second device regions. The first device region contains an entirety of a first active area of a first logic device, the second device region contains an entirety of a second active area of a second logic device, and the second device region shares a boundary with the first device region. The semiconductor structure also includes a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary, and a via contacting the first metal zero pin. A distance from the center of the via to the boundary is less than or equal to a first predetermined distance, and the via is electrically connected to one of the first logic device or the second logic device.

    Scan Flip-Flops With Pre-Setting Combinational Logic
    10.
    发明公开
    Scan Flip-Flops With Pre-Setting Combinational Logic 审中-公开

    公开(公告)号：US20240077534A1

    公开(公告)日：2024-03-07

    申请号：US18150830

    申请日：2023-01-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

    IPC: G01R31/3185

    CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318555

    Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

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