Invention Publication
- Patent Title: Scan Flip-Flops With Pre-Setting Combinational Logic
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Application No.: US18150830Application Date: 2023-01-06
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Publication No.: US20240077534A1Publication Date: 2024-03-07
- Inventor: Johnny Chiahao Li , Sheng-Hsiung Chen , Tzu-Ying Lin , Yung-Chen Chien , Jerry Chang Jui Kao , Xiangdong Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: G01R31/3185
- IPC: G01R31/3185

Abstract:
Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.
Public/Granted literature
- US12066489B2 Scan flip-flops with pre-setting combinational logic Public/Granted day:2024-08-20
Information query
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