公开(公告)号：US20240361383A1

公开(公告)日：2024-10-31

申请号：US18770809

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318541 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US12081215B2

公开(公告)日：2024-09-03

申请号：US18333284

申请日：2023-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lun Ou ,  Ji-Yung Lin ,  Yung-Chen Chien ,  Ruei-Wun Sun ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

公开(公告)号：US20210099161A1

公开(公告)日：2021-04-01

申请号：US17026423

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US12199612B2

公开(公告)日：2025-01-14

申请号：US17858844

申请日：2022-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Xing Chao Yin ,  Huaixin Xian ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H03K3/037 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

Abstract: A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

公开(公告)号：US11757435B2

公开(公告)日：2023-09-12

申请号：US17815679

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chi Huang ,  Yung-Chen Chien ,  Chi-Lin Liu ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  G06F1/3237 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/0375 ,  G06F1/3237 ,  H03K3/0372 ,  H03K3/356086 ,  H03K19/0016

Abstract: A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.

公开(公告)号：US11677400B2

公开(公告)日：2023-06-13

申请号：US17835906

申请日：2022-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lun Ou ,  Ji-Yung Lin ,  Yung-Chen Chien ,  Ruei-Wun Sun ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

公开(公告)号：US20240333265A1

公开(公告)日：2024-10-03

申请号：US18738225

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177 ,  H03K19/20

CPC classification number: H03K3/0372 ,  G01R31/31725 ,  G01R31/3177 ,  H03K19/20

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US12107581B2

公开(公告)日：2024-10-01

申请号：US18362916

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

公开(公告)号：US12047079B2

公开(公告)日：2024-07-23

申请号：US18302178

申请日：2023-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chen Chien ,  Xiangdong Chen ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao ,  Lee-Chung Lu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

公开(公告)号：US20240077534A1

公开(公告)日：2024-03-07

申请号：US18150830

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.