公开(公告)号：US12085611B2

公开(公告)日：2024-09-10

申请号：US17285614

申请日：2018-10-16

申请人： Minima Processor Oy

发明人： Lauri Koskinen ,  Navneet Gupta ,  Jesse Simonsson

IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/3173

CPC分类号： G01R31/3177 ,  G01R31/31712 ,  G01R31/31725 ,  G01R31/3173

摘要： The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value. The method comprises making said one or more adaptive processing paths form test output values on the basis of the respective test input values input to them, and forming a set of test output signals by collecting said test output values given by said one or more adaptive processing paths. The method comprises examining said set of test output signals, and forming a test result on the basis of said examining, and using said test result to select and set an operating parameter value for said operating parameter.

公开(公告)号：US20240288831A1

公开(公告)日：2024-08-29

申请号：US18173560

申请日：2023-02-23

申请人： Meta Platforms Technologies, LLC

发明人： Sri Harsha Manjunath

IPC分类号： G01R31/317

CPC分类号： G04F10/00 ,  G01R31/31725 ,  G01R31/31727

摘要： A method implemented by a multi-chip package (MCP) electronic device including a die-to-die (D2D) interface is provided. The method includes receiving, by a receiver portion of a first die of the D2D interface, and from a transmitter portion of a second die of the D2D interface, a first timing signal and a second timing signal. The method includes performing a calibration of the second timing signal by generating a timing calibration signal based on a timing value corresponding to a midpoint of an estimated margin between overlaying segments of the first timing signal and a timing value corresponding to a delay of a unit delay of an oscillator associated with the receiver portion and outputting the timing calibration signal. The timing calibration signal is configured to cause a rising edge of the second timing signal to correspond to a midpoint of a pulse width of the first timing signal.

公开(公告)号：US20240288494A1

公开(公告)日：2024-08-29

申请号：US18173548

申请日：2023-02-23

申请人： Meta Platforms Technologies, LLC

发明人： Sri Harsha Manjunath

IPC分类号： G01R31/317

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A method implemented by a multi-chip package (MCP) electronic device including a die-to-die (D2D) interface is provided. The method includes receiving, by a receiver portion of a first die of the D2D interface, and from a transmitter portion of a second die of the D2D interface, a first timing signal and a second timing signal. The method includes performing a first calibration of one or more of the first timing signal or the second timing signal. The first calibration is configured to align a first rising edge of the first timing signal with a second rising edge of the second timing signal. The method includes performing a second calibration of the second timing signal. The second calibration is configured to offset the second rising edge of the second timing signal with respect to the first rising edge of the first timing signal by a predetermined time period.

公开(公告)号：US20240183902A1

公开(公告)日：2024-06-06

申请号：US18526943

申请日：2023-12-01

申请人： Lattice Semiconductor Corporation

发明人： Maryam Shahbazi ,  Bradley A. Sharpe-Geisler ,  Senani Gunaratna ,  Loren L. McLaury

IPC分类号： G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/318594

摘要： Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.

公开(公告)号：US20240110976A1

公开(公告)日：2024-04-04

申请号：US18376001

申请日：2023-10-03

申请人： Realtek Semiconductor Corp.

发明人： Ching-Feng Huang ,  Yu-Cheng Lo

IPC分类号： G01R31/317

CPC分类号： G01R31/31727 ,  G01R31/31721 ,  G01R31/31725

摘要： An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

公开(公告)号：US11921158B2

公开(公告)日：2024-03-05

申请号：US18075542

申请日：2022-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： Byung-Sung Kim ,  Yun-Hyok Choi ,  Gyuyeol Kim ,  Sungjung Kim ,  Cheol-Heui Park ,  Sanghoon Lee ,  Jae-Woong Choi

IPC分类号： G01R31/3177 ,  G01R1/073 ,  G01R23/165 ,  G01R25/04 ,  G01R31/317 ,  G01R31/3183 ,  G04F10/00

CPC分类号： G01R31/3177 ,  G01R1/07314 ,  G01R23/165 ,  G01R25/04 ,  G01R31/31713 ,  G01R31/31715 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318328 ,  G04F10/005

摘要： Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

公开(公告)号：US11894848B2

公开(公告)日：2024-02-06

申请号：US17311186

申请日：2018-12-05

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta ,  Lauri Koskinen

IPC分类号： H03K3/037 ,  G01R31/317 ,  G01R31/3177

CPC分类号： H03K3/037 ,  G01R31/3177 ,  G01R31/31725

摘要： A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

公开(公告)号：US20240019489A1

公开(公告)日：2024-01-18

申请号：US18373447

申请日：2023-09-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/317 ,  G06F11/27 ,  G01R31/3185 ,  G01R31/3177 ,  G06F11/267

CPC分类号： G01R31/31723 ,  G06F11/27 ,  G01R31/31727 ,  G01R31/318572 ,  G01R31/3177 ,  G01R31/31722 ,  G01R31/31725 ,  G06F11/267 ,  G06F11/261

摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US11867744B2

公开(公告)日：2024-01-09

申请号：US17075629

申请日：2020-10-20

申请人： NVIDIA CORPORATION

发明人： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg ,  Sailendra Chadalavada

IPC分类号： G01R31/26 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F13/42

CPC分类号： G01R31/2601 ,  G01R31/2639 ,  G01R31/31725 ,  G01R31/318328 ,  G01R31/318536 ,  G06F13/4221 ,  G06F2213/0026

摘要： Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

公开(公告)号：US20230393196A1

公开(公告)日：2023-12-07

申请号：US18089541

申请日：2022-12-27

申请人： PROTEANTECS LTD.

发明人： Eyal FAYNEH ,  Guy REDLER ,  Evelyn LANDMAN

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/2882

摘要： An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.