- 专利标题: ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES
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申请号: US18173548申请日: 2023-02-23
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公开(公告)号: US20240288494A1公开(公告)日: 2024-08-29
- 发明人: Sri Harsha Manjunath
- 申请人: Meta Platforms Technologies, LLC
- 申请人地址: US CA Menlo Park
- 专利权人: Meta Platforms Technologies, LLC
- 当前专利权人: Meta Platforms Technologies, LLC
- 当前专利权人地址: US CA Menlo Park
- 主分类号: G01R31/317
- IPC分类号: G01R31/317
摘要:
A method implemented by a multi-chip package (MCP) electronic device including a die-to-die (D2D) interface is provided. The method includes receiving, by a receiver portion of a first die of the D2D interface, and from a transmitter portion of a second die of the D2D interface, a first timing signal and a second timing signal. The method includes performing a first calibration of one or more of the first timing signal or the second timing signal. The first calibration is configured to align a first rising edge of the first timing signal with a second rising edge of the second timing signal. The method includes performing a second calibration of the second timing signal. The second calibration is configured to offset the second rising edge of the second timing signal with respect to the first rising edge of the first timing signal by a predetermined time period.
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