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公开(公告)号：US20240319269A1
公开(公告)日：2024-09-26
申请号：US18124338
申请日：2023-03-21
申请人： Intel Corporation
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/31725 , G01R31/31713 , G01R31/318536
摘要： An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.
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公开(公告)号：US12050248B2
公开(公告)日：2024-07-30
申请号：US18304691
申请日：2023-04-21
发明人： Yu Huang , Weiwei Zhang
IPC分类号： G01R31/3183 , G01R31/28 , G01R31/317 , G01R31/3177 , G01R31/3185 , H03K19/173 , H03K19/21
CPC分类号： G01R31/318335 , G01R31/31713 , G01R31/3177 , G01R31/318536 , H03K19/1733 , H03K19/21 , G01R31/2834
摘要： This application provides decompression circuits. An example decompression circuit includes a plurality of sub-circuits. The sub-circuit includes a plurality of cellular automaton (CA) circuits and a phase shifter. Each of the plurality of CA circuits includes a first XOR circuit and a register. The first XOR circuit includes a first input end, a second input end, and an output end. A data input end of the register is coupled to the output end of the first XOR circuit. A data output end of the register is coupled to the first input end of the first XOR circuit and an input end of the phase shifter. The data output end of the register is further coupled to the second input end of the first XOR circuit in a different CA circuit. The phase shifter is configured to output a test signal.
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公开(公告)号：US11988710B2
公开(公告)日：2024-05-21
申请号：US17166956
申请日：2021-02-03
发明人： Chia-Chi Hsu
IPC分类号： G01R31/28 , G01R23/02 , G01R31/317 , G06F11/26 , G06F11/267 , G06F11/273
CPC分类号： G01R31/31713 , G06F11/267 , G06F11/273
摘要： The present invention provides a test method, a tester, a load board and a test system. The test method includes: outputting, through a first input/output (I/O) port of a tester, a first test signal to a first channel of a load board, wherein the first test signal is used to generate a second test signal and a third test signal; receiving, through the first I/O port, a third feedback signal returned from the first channel, wherein the third feedback signal is generated based on a first feedback signal and a second feedback signal; and determining whether a first chip and a second chip are operating normally based on the third feedback signal. Solutions provided in the present invention are capable of increasing the number of chips that can be tested at a single time.
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公开(公告)号：US11966132B2
公开(公告)日：2024-04-23
申请号：US17479206
申请日：2021-09-20
申请人： Japan Display Inc.
发明人： Keita Sasanuma , Kengo Shiragami , Naoyuki Obinata
IPC分类号： G02F1/1362 , G01R31/317 , G02F1/1345 , G02F1/1368
CPC分类号： G02F1/136254 , G01R31/31713 , G02F1/13456 , G02F1/13452 , G02F1/1368
摘要： A display device includes signal lines, first driver terminals that are provided in a first peripheral region and to which a first driver IC can be coupled, second driver terminals to which a second driver IC can be coupled, a plurality of inspection terminals provided in the first peripheral region, first inspection switches coupled to the first driver terminals and configured to be capable of switching coupling and interruption of the inspection terminals and the signal lines, and second inspection switches coupled to the second driver terminals and configured to be capable of switching coupling and interruption of the inspection terminals and the signal lines.
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公开(公告)号：US20240072777A1
公开(公告)日：2024-02-29
申请号：US18447955
申请日：2023-08-10
发明人： Nick Samra , Stefan Rusu , Ta-Pen Guo
IPC分类号： H03K3/037 , G01R31/317 , G01R31/3177 , G11C11/412 , G11C11/419
CPC分类号： H03K3/0372 , G01R31/31713 , G01R31/3177 , G11C11/412 , G11C11/419 , G11C11/418
摘要： A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
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公开(公告)号：US11899061B2
公开(公告)日：2024-02-13
申请号：US17347284
申请日：2021-06-14
申请人： Apple Inc.
发明人： Fabien S. Faure , Si Chen , Mansour Keramat , Arnaud J. Forestier
CPC分类号： G01R31/31713 , G01R13/029 , G01R13/0272 , G01R19/2503 , G01R31/31705 , G06F11/10 , H03M1/12
摘要： A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.
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公开(公告)号：US11847059B2
公开(公告)日：2023-12-19
申请号：US17809136
申请日：2022-06-27
发明人： David Andrew Roberts
IPC分类号： G11C5/06 , G06F12/06 , G01R31/317 , G06F11/10 , G06F12/0882 , G06F12/0868 , G06F9/54 , G06F11/30 , G06F9/50
CPC分类号： G06F12/0882 , G06F9/5016 , G06F9/546 , G06F11/1004 , G06F11/1068 , G06F11/3037 , G06F12/06 , G06F12/0868 , G11C5/066 , G01R31/31713
摘要： Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.
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公开(公告)号：US20230400514A1
公开(公告)日：2023-12-14
申请号：US18177809
申请日：2023-03-03
申请人： Kioxia Corporation
发明人： Kazuhiko NAKAHARA
IPC分类号： G01R31/3185 , G01R31/317 , G01R31/28
CPC分类号： G01R31/318508 , G01R31/31713 , G01R31/2863
摘要： According to a certain embodiment, the test system includes a first test board, a test executable integrated circuit, and a first measuring apparatus. A device under test (DUT) is mounted on the first test board. The test executable integrated circuit is mounted on the first test board, and is configured to read firmware stored in the DUT in advance and to test the DUT. The first measuring apparatus instructs the test executable integrated circuit to start a test of the DUT. There are provided the test system, the test method, and the non-transitory computer readable medium, capable of reducing costs required for tests and also of shortening test time.
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公开(公告)号：US20230400511A1
公开(公告)日：2023-12-14
申请号：US17843837
申请日：2022-06-17
发明人： Jin-Dong Zhao
IPC分类号： G01R31/317
CPC分类号： G01R31/31715 , G01R31/31713
摘要： A pin testing system for a multi-pin chip and method thereof are disclosed. In the system, a chip testing circuit board includes a testing circuit, a to-be-tested chip fixture, a testing chip and a JTAG port, each pin of the testing chip is electrically connected to a corresponding pin of the to-be-tested chip fixture through the testing circuit. The JTAG port, the testing chip and the to-be-tested chip fixture are serially connected to form a JTAG link through the testing circuit, the testing device, the JTAG controller and the chip testing circuit board are serially connected, the testing device generates a testing signal to test each of the pins of the to-be-tested chip through the JTAG controller, and a testing result for each of the pins is transmitted to the testing device, so that the testing on the pins of the to-be-tested chip is completed.
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公开(公告)号：US11836084B2
公开(公告)日：2023-12-05
申请号：US17809126
申请日：2022-06-27
发明人： David Andrew Roberts
IPC分类号： G11C5/06 , G06F12/06 , G06F11/10 , G06F12/0882 , G06F12/0868 , G06F9/54 , G06F11/30 , G06F9/50 , G01R31/317
CPC分类号： G06F12/0882 , G06F9/5016 , G06F9/546 , G06F11/1004 , G06F11/1068 , G06F11/3037 , G06F12/06 , G06F12/0868 , G11C5/066 , G01R31/31713
摘要： Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.
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