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    Scan Tree Construction
    1.
    发明公开
    Scan Tree Construction 审中-公开

    公开(公告)号：US20240151771A1

    公开(公告)日：2024-05-09

    申请号：US18115777

    申请日：2023-03-01

    申请人： TSINGHUA UNIVERSITY

    发明人： Can Xiang ,  Dong Xiang

    IPC分类号： G01R31/3185 ,  G01R31/28 ,  G01R31/3183

    CPC分类号： G01R31/318536 ,  G01R31/2834 ,  G01R31/318321 ,  G01R31/318335

    摘要： Scan forest can effectively compress test data volume, however, CPU time and memory consumption must be well-controlled to handle industrial designs. The present disclosure provides a method to establish a scan forest, which reduces memory consumption and CPU time significantly. A new low-power test application scheme is proposed, which does not need to increase the test application cost but can be of help to compress test data volume. Another new test application algorithm is proposed to reduce capture cycle power and shift cycle power by just doubling the test application time, which does not sacrifice the test data compression performance.

    Remote test management of digital logic circuits
    5.
    发明授权
    Remote test management of digital logic circuits 有权

    公开(公告)号：US09952278B2

    公开(公告)日：2018-04-24

    申请号：US15114472

    申请日：2014-02-05

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Elena Dubrova ,  Gunnar Carlsson ,  John Fornehed ,  Mats Näslund ,  Bernard Smeets

    IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3183

    CPC分类号： G01R31/2884 ,  G01R31/31813 ,  G01R31/318335 ,  G01R31/318385

    摘要： Electronic devices (320) are provided which comprise a digital logic circuit (101) and a test module (322) adapted to receive test parameters from a remote test management device (310), generate test patterns based on the test parameters, apply the test patterns to the digital logic circuit, receive test responses from the digital logic circuit, compact the test responses into a test signature, and either transmit the test signature to the remote test management device or determine a test result based on a comparison of an expected signature received from the remote test management device with the test signature. Further provided are remote test management devices comprising means adapted to acquire test parameters suitable for generating test patterns for a digital logic circuit, acquire an expected signature corresponding to the test patterns, transmit the test parameters to at least one electronic device comprising the digital logic circuit, and either receive a test signature from the at least one electronic device and determine a test result based on a comparison of the expected signature with the test signature, or transmit the expected signature to the at least one electronic device.

    Physically aware insertion of diagnostic circuit elements
    9.
    发明授权
    Physically aware insertion of diagnostic circuit elements 有权
    诊断电路元件的物理意识插入

    公开(公告)号：US09557381B1

    公开(公告)日：2017-01-31

    申请号：US14987824

    申请日：2016-01-05

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： William V. Huott ,  Mary P. Kusko ,  Sridhar H. Rangarajan ,  Robert C. Redburn ,  Andrew A. Turner

    IPC分类号： G01R31/3185 ,  G01R31/3183 ,  G01R31/3177

    CPC分类号： G01R31/318541 ,  G01R31/318335 ,  G01R31/318536 ,  G01R31/318563 ,  G01R31/318572 ,  G06F17/5045 ,  G06F17/5072

    摘要： According to an embodiment of the present invention, a computer-implemented method for inserting diagnostic circuit elements in a scan chain of a chip may include creating, via a processor, a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments, merging, via the processor, the two adjacent and connected segments to form a super-segment comprising all latches contained in the two adjacent and connected segments based on the objective function, and inserting, via the processor, a logic circuit element between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, where the logic circuit element allows diagnostic isolation of the scan chain super-segment.

    摘要翻译： 根据本发明的实施例，用于在芯片的扫描链中插入诊断电路元件的计算机实现的方法可以包括经由处理器为扫描链中的多个锁存器的每个锁存器创建段，以创建 多个相邻和连接的段，经由处理器合并两个相邻和连接的段，以形成包含基于目标函数的包含在两个相邻和连接段中的所有锁存器的超级段，并且经由处理器插入， 超级段和与扫描链中的超级段相邻并连接的段的逻辑电路元件，其中逻辑电路元件允许扫描链超级段的诊断隔离。

    Programmable access test compression architecture input and output shift registers
    10.
    发明授权
    Programmable access test compression architecture input and output shift registers 有权
    可编程访问测试压缩架构输入和输出移位寄存器

    公开(公告)号：US09360521B2

    公开(公告)日：2016-06-07

    申请号：US14625351

    申请日：2015-02-18

    申请人： Texas Instruments Incorporated

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/273

    CPC分类号： G01R31/318335 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/2733

    摘要： The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

    摘要翻译： 本公开描述了使用并行或串行访问技术在设备中访问测试压缩架构（TCA）的新颖的方法和装置。 串行访问技术可以由设备测试者或JTAG控制器控制。 此外，本公开提供了当设备以与其他设备（例如客户系统）中的菊花链布置存在时访问设备的TCA的方法。 在本公开中还提供和描述了另外的实施例。