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    Digital power on reset circuit and method
    1.
    发明授权
    Digital power on reset circuit and method 有权

    公开(公告)号：US12231116B1

    公开(公告)日：2025-02-18

    申请号：US18505262

    申请日：2023-11-09

    Applicant: Ciena Corporation

    Inventor： Daryl Anthony Boyd ,  Derek R. Mudd

    IPC: H03K17/22 ,  G01R31/3185

    Abstract: A digital Power on Reset (POR) circuit includes N counters; N comparators each connected to an output of a corresponding counter of the N counters to compare with a corresponding specific value, N is an integer greater than or equal to 1; and a comparison block connected to an output of each of the N comparators and configured to output a reset signal based on the output of each of the N comparators. The digital POR circuit utilizes a complete digital design, enabling efficient integration with a processing circuit. The digital POR circuit can utilize the same libraries, cells, etc. as other digital components in the processing circuit, and can be tested with other digital components in the processing circuit.

    MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON DIAGNOSTIC CODE SEQUENCE
    3.
    发明申请
    MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON DIAGNOSTIC CODE SEQUENCE 有权

    公开(公告)号：US20250027996A1

    公开(公告)日：2025-01-23

    申请号：US18482703

    申请日：2023-10-06

    Applicant: QUALCOMM Incorporated

    Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

    IPC: G01R31/3185

    Abstract: Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an apparatus includes an integrated circuit having a logic path formed in the integrated circuit and a monitor circuit formed in the integrated circuit. The monitor circuit is configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic code sequence.

    CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
    4.
    发明申请
    CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS 有权

    公开(公告)号：US20250027995A1

    公开(公告)日：2025-01-23

    申请号：US18908311

    申请日：2024-10-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

    Chip test circuit and circuit test method
    7.
    发明授权
    Chip test circuit and circuit test method 有权

    公开(公告)号：US12181519B2

    公开(公告)日：2024-12-31

    申请号：US18175306

    申请日：2023-02-27

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Changming Cui ,  Junlin Huang ,  Yu Huang ,  Haitao Fu

    IPC: G01R31/317 ,  G01R31/3185

    Abstract: This disclosure provides methods and apparatuses for testing a tested circuit. In an implementation, a chip test circuit transmits input data of a test vector to a data distribution circuit through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit through the data distribution circuit. After scanning of the tested circuit ends, output data of the test vector of the scan output channel of the tested circuit is transmitted to an output of the test bus through the data distribution circuit to complete the test of the tested circuit. A dynamic correspondence between the data distribution circuit and the test bus is implemented by configuring a first selector, so that test resources can be dynamically allocated.

    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
    10.
    发明申请
    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT 有权

    公开(公告)号：US20240402247A1

    公开(公告)日：2024-12-05

    申请号：US18799555

    申请日：2024-08-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/267 ,  G06F11/27 ,  G06F11/34

    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

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