公开(公告)号：US20250028377A1

公开(公告)日：2025-01-23

申请号：US18482749

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G06F1/3228 ,  G06F1/3296 ,  G06F11/27

Abstract: Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

公开(公告)号：US20250027996A1

公开(公告)日：2025-01-23

申请号：US18482703

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G01R31/3185

Abstract: Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an apparatus includes an integrated circuit having a logic path formed in the integrated circuit and a monitor circuit formed in the integrated circuit. The monitor circuit is configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic code sequence.

公开(公告)号：US20250028890A1

公开(公告)日：2025-01-23

申请号：US18482681

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G06F30/343 ,  G06F30/327

Abstract: Aspects relate to monitoring timing. In one example an apparatus includes a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit and sensors of the first sensor array configured to generate one or more first level indications of a condition of the integrated circuit. A second sensor array is formed in the integrated circuit. Sensors of the second sensor array have paths through the integrated circuit and sensors of the second sensor array are configured to generate one or more second level indications of the condition of the integrated circuit. A monitor controller is coupled to the first sensor array and to the second sensor array and configured to receive the one or more first level indications and to actuate the second sensor array in response to the one or more first level indications.