公开(公告)号：US12231116B1

公开(公告)日：2025-02-18

申请号：US18505262

申请日：2023-11-09

Applicant: Ciena Corporation

Inventor： Daryl Anthony Boyd ,  Derek R. Mudd

IPC: H03K17/22 ,  G01R31/3185

Abstract: A digital Power on Reset (POR) circuit includes N counters; N comparators each connected to an output of a corresponding counter of the N counters to compare with a corresponding specific value, N is an integer greater than or equal to 1; and a comparison block connected to an output of each of the N comparators and configured to output a reset signal based on the output of each of the N comparators. The digital POR circuit utilizes a complete digital design, enabling efficient integration with a processing circuit. The digital POR circuit can utilize the same libraries, cells, etc. as other digital components in the processing circuit, and can be tested with other digital components in the processing circuit.