公开(公告)号：US20230100019A1

公开(公告)日：2023-03-30

申请号：US17490241

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Gokul Sabada

IPC: H03K3/037

Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

公开(公告)号：US20250027995A1

公开(公告)日：2025-01-23

申请号：US18908311

申请日：2024-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

公开(公告)号：US12146912B1

公开(公告)日：2024-11-19

申请号：US18308486

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

公开(公告)号：US11043937B1

公开(公告)日：2021-06-22

申请号：US16713343

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Arnab Khawas ,  Suvam Nandi

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US11946973B1

公开(公告)日：2024-04-02

申请号：US18071208

申请日：2022-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Madhavan Sainath Rao Pissay

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318572 ,  G01R31/318552 ,  G01R31/31926

Abstract: In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.

公开(公告)号：US11916555B2

公开(公告)日：2024-02-27

申请号：US17490241

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Gokul Sabada

IPC: H03K3/037 ,  H03K3/012

CPC classification number: H03K3/037 ,  H03K3/012 ,  H03K3/0372

Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

公开(公告)号：US20220342634A1

公开(公告)日：2022-10-27

申请号：US17241753

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Nandini Bollam ,  Badarish Mohan Subbannavar

IPC: G06F7/501 ,  H03K17/687

Abstract: Examples of compact, high performance full adder circuits and methods of forming and operating the same are provided. In an example, a full adder comprises a first stage, a second stage and a third stage. The first stage has a first output at which a first reused signal is generated and a second output at which a second reused signal is generated. The second stage has a first reused signal input to which the first reused signal is applied, a second reused signal input to which the second reused signal is applied, and a sum output at which a sum signal is generated. The third stage has a third reused signal input to which the first reused signal is applied, a fourth reused signal input to which the second reused signal is applied, and a carry-out output at which a carry-out signal is generated. In some examples, the first stage includes a transistor stack and an inverter that share a transistor.

公开(公告)号：US20240361384A1

公开(公告)日：2024-10-31

申请号：US18308486

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318552 ,  G01R31/31724 ,  G01R31/31727

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

公开(公告)号：US20240210472A1

公开(公告)日：2024-06-27

申请号：US18597215

申请日：2024-03-06

Applicant: Texas Instruments Incorporated

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Madhavan Sainath Rao Pissay

IPC: G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318572 ,  G01R31/318552 ,  G01R31/31926

Abstract: In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.

公开(公告)号：US11509294B2

公开(公告)日：2022-11-22

申请号：US17319505

申请日：2021-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Arnab Khawas ,  Suvam Nandi

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.