公开(公告)号：US20230100019A1

公开(公告)日：2023-03-30

申请号：US17490241

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Gokul Sabada

IPC: H03K3/037

Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

公开(公告)号：US20250027995A1

公开(公告)日：2025-01-23

申请号：US18908311

申请日：2024-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

公开(公告)号：US11916555B2

公开(公告)日：2024-02-27

申请号：US17490241

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Badarish Subbannavar ,  Gokul Sabada

IPC: H03K3/037 ,  H03K3/012

CPC classification number: H03K3/037 ,  H03K3/012 ,  H03K3/0372

Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

公开(公告)号：US12146912B1

公开(公告)日：2024-11-19

申请号：US18308486

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

公开(公告)号：US20240361384A1

公开(公告)日：2024-10-31

申请号：US18308486

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Gokul Sabada ,  Madhavan Sainath Rao Pissay ,  Badarish Subbannavar

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318552 ,  G01R31/31724 ,  G01R31/31727

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.