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    Scan wrapper circuit for integrated circuit
    2.
    发明授权
    Scan wrapper circuit for integrated circuit 有权
    用于集成电路的扫描包装电路

    公开(公告)号：US09568551B1

    公开(公告)日：2017-02-14

    申请号：US14855396

    申请日：2015-09-16

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Sagar Kataria ,  Anurag Jindal ,  Abhishek Mahajan ,  Mayank Parasrampuria

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/318558 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318552 ,  G01R31/318572

    Abstract: An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.

    Abstract translation: 在内部和外部测试模式（INTEST和EXTEST）中可操作的集成电路（IC）包括第一和第二分区以及它们之间的功能路径。 第一分区包括第一扫描链，第一多路复用器和第一触发器。 第二分区包括第二触发器和第二扫描链。 第一个扫描链基于EXTEST扫描输入信号产生EXTEST矢量初始化信号。 第一多路复用器接收INTEST向量初始化信号和EXTEST向量初始化信号，并产生扫描输入信号。 第一触发器基于扫描输入信号产生第一输出信号。 功能路径基于第一输出信号提供第二输出信号。 第二触发器基于第二输出信号产生第三输出信号。 第二扫描链接收第三输出信号并产生测试输出信号。

    Interconnections for Plural and Hierarchical P1500 Test Wrappers
    5.
    发明申请
    Interconnections for Plural and Hierarchical P1500 Test Wrappers 有权
    多层和分层P1500测试包装机的互连

    公开(公告)号：US20130268816A1

    公开(公告)日：2013-10-10

    申请号：US13909416

    申请日：2013-06-04

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

    Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.—The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

    Abstract translation: 测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器位于核心的边界处，并提供了一种测试核心和核心之间的互连的方法。测试架构使得IC中的多个包装器中的每个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号 。

    Interconnections for Plural and Hierarchical P1500 Test Wrappers
    6.
    发明申请
    Interconnections for Plural and Hierarchical P1500 Test Wrappers 有权
    多层和分层P1500测试包装机的互连

    公开(公告)号：US20130254610A1

    公开(公告)日：2013-09-26

    申请号：US13892473

    申请日：2013-05-13

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

    Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

    Abstract translation: 测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器位于核心的边界处，并提供了一种测试核心和核心之间互连的方法。 测试架构使得IC中的多个包装器中的每一个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号。

    TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS
    7.
    发明申请
    TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS 有权
    用于基于TSV的3D堆叠ICS的测试访问架构

    公开(公告)号：US20130024737A1

    公开(公告)日：2013-01-24

    申请号：US13626538

    申请日：2012-09-25

    Applicant: IMEC ,  Stichting IMEC Nederland

    Inventor： Erik Jan Marinissen ,  Jacobus Verbree ,  Mario Konijnenburg ,  Chun-Chuan Chi

    IPC: G01R31/3177

    CPC classification number: G01R31/318508 ,  G01R31/31717 ,  G01R31/3177 ,  G01R31/318511 ,  G01R31/318513 ,  G01R31/318572

    Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

    Abstract translation: 公开了用于3D-SIC的测试访问架构，其允许预键合芯片测试和后绑定堆叠测试。 测试访问架构基于模块化测试方法，其中各种模具，其嵌入式IP内核，基于芯片间TSV的互连和外部I / O可以作为单独的单元进行测试，从而优化3D -SIC测试流程。 该架构建立并重用现有的核心，管芯和产品级测试（DfT）硬件设计。 通过称为包装单元的测试结构将测试访问提供给单个管芯堆叠。

    Input-output device testing including voltage tests
    9.
    发明授权
    Input-output device testing including voltage tests 有权
    输入输出设备测试，包括电压测试

    公开(公告)号：US08032805B1

    公开(公告)日：2011-10-04

    申请号：US11520276

    申请日：2006-09-12

    Applicant: Sassan Tabatabaei

    Inventor： Sassan Tabatabaei

    IPC: G01R31/28

    CPC classification number: G01R31/318572 ,  G01R31/318508

    Abstract: Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

    Abstract translation: 集成电路可以至少包括指令处理器和输入输出子系统。 每个输入 - 输出子系统包括由指令处理器控制的包装电路的包装电路。 包装电路包括两个或更多个扫描寄存器，其中存储在每个扫描寄存器中的数据值可以被移出以用于分析。 封装电路还包括两个或多个更新寄存器，用于在其自身与相关联的扫描寄存器之间传送存储的数据值。 包装电路还包括耦合到扫描寄存器，更新寄存器和指令测试处理器的一组组合逻辑，其中多个I / O中的至少两个I / O，但是小于所有多个I / O 耦合到外部测试仪。

    Interconnections for plural and hierarchical P1500 test wrappers
    10.
    发明授权
    Interconnections for plural and hierarchical P1500 test wrappers 有权
    多个和分层P1500测试包装器的互连

    公开(公告)号：US07913135B2

    公开(公告)日：2011-03-22

    申请号：US12887664

    申请日：2010-09-22

    Applicant: Lee D. Whetsel

    Inventor： Lee D. Whetsel

    IPC: G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

    Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.-The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

    Abstract translation: 测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器位于核心的边界处，并提供了一种测试核心和核心之间的互连的方法。测试架构使得IC中的多个包装器中的每个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号 。

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