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    PARALLEL RAS CHANNELS IN CXL MEMORY DEVICE
    2.
    发明公开
    PARALLEL RAS CHANNELS IN CXL MEMORY DEVICE 审中-公开

    公开(公告)号：US20240345982A1

    公开(公告)日：2024-10-17

    申请号：US18444550

    申请日：2024-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Nikesh AGARWAL ,  Chandana MANJULA LINGANNA

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4221 ,  G06F13/1642

    Abstract: A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.

    Data processing unit with transparent root complex
    3.
    发明授权
    Data processing unit with transparent root complex 有权

    公开(公告)号：US12117948B2

    公开(公告)日：2024-10-15

    申请号：US17976909

    申请日：2022-10-31

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

    IPC: G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

    Synchronizing systems on a chip using a shared clock
    4.
    发明授权
    Synchronizing systems on a chip using a shared clock 有权

    公开(公告)号：US12105553B2

    公开(公告)日：2024-10-01

    申请号：US18236732

    申请日：2023-08-22

    Applicant: Snap Inc.

    Inventor： Samuel Ahn ,  Jason Heger ,  Dmitry Ryuma

    IPC: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/16 ,  G06F3/01 ,  G06F13/42 ,  G06F15/173

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/163 ,  G06F3/011 ,  G06F13/4221 ,  G06F15/17325 ,  G06F2213/0026

    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

    Multiple port emulation
    6.
    发明授权
    Multiple port emulation 有权

    公开(公告)号：US12093706B2

    公开(公告)日：2024-09-17

    申请号：US18186748

    申请日：2023-03-20

    Applicant: Amazon Technologies, Inc.

    Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

    IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

    CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

    Memory system and host device
    7.
    发明授权
    Memory system and host device 有权

    公开(公告)号：US12086068B2

    公开(公告)日：2024-09-10

    申请号：US18190135

    申请日：2023-03-27

    Applicant: SK hynix Inc.

    Inventor： Sung Woo Hyun

    IPC: G06F12/0862 ,  G06F12/0804 ,  G06F13/42

    CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F13/4221

    Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.

    Data Storage Devices with Services to Manage File Storage Locations
    8.
    发明公开
    Data Storage Devices with Services to Manage File Storage Locations 审中-公开

    公开(公告)号：US20240289271A1

    公开(公告)日：2024-08-29

    申请号：US18439696

    申请日：2024-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F12/02 ,  G06F12/06 ,  G06F13/42

    CPC classification number: G06F12/0246 ,  G06F12/063 ,  G06F13/4221

    Abstract: Memory sub-systems configured to manage storage locations of files for a host system. For example, a connection from a memory sub-system to the host system can support both a cache-coherent memory access protocol to a memory device implemented in the storage capacity of the memory sub-system and a storage access protocol. The memory sub-system can maintain, and share with the host system via the memory device, a medium map configured to identify, for a file stored in the memory sub-system, memory addresses usable for the host system to access locations in the file over the connection using the cache-coherent memory access protocol, and/or logical block addresses usable for the host system to access blocks of the files over the connection using the storage access protocol.

    Synchronous/Asynchronous Network Communications Layer
    10.
    发明公开
    Synchronous/Asynchronous Network Communications Layer 审中-公开

    公开(公告)号：US20240264968A1

    公开(公告)日：2024-08-08

    申请号：US18104872

    申请日：2023-02-02

    Applicant: Dell Products L.P.

    Inventor： Paul A. Linstead ,  Doug E. Lecrone

    IPC: G06F13/42

    CPC classification number: G06F13/4221 ,  G06F2213/0026

    Abstract: One or more aspects of the present disclosure relate to establishing and using a hybrid synchronous/asynchronous communication layer for input/output (IO) messages to a storage array. In embodiments, an input/output (IO) message can be modified into first and second IO portions. In addition, a network communications layer can be established to include synchronous and asynchronous channels. Further, the first IO portion can be transmitted over the synchronous channel, and the second IO portion can be transmitted over the asynchronous channel.

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