公开(公告)号：US11855757B1

公开(公告)日：2023-12-26

申请号：US17643785

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Julien Ridoux ,  Joshua Benjamin Levinson ,  Said Bshara ,  Erez Izenberg ,  Robert Klein ,  Alan Michael Judge

IPC: G06F1/10 ,  G06F1/12 ,  H04J3/06

CPC classification number: H04J3/0644 ,  G06F1/10 ,  G06F1/12

Abstract: Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

公开(公告)号：US11650835B1

公开(公告)日：2023-05-16

申请号：US16836527

申请日：2020-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/45 ,  G06F9/455 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

公开(公告)号：US09411731B2

公开(公告)日：2016-08-09

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US12026103B1

公开(公告)日：2024-07-02

申请号：US17444352

申请日：2021-08-03

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara ,  Alexander Matushevsky

IPC: G06F13/00 ,  G06F3/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/16 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/067 ,  G06F9/45558 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: A resource request is received by a peripheral device from host processing logic. The resource request includes a requested resource size. The peripheral device allocates resource of the peripheral device in response to the resource request. A resource response is sent by the peripheral device to the host processing logic. The resource response includes a location of the allocated resource.

公开(公告)号：US20240111562A1

公开(公告)日：2024-04-04

申请号：US17957939

申请日：2022-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Evgeny Schmeilin ,  Dileep Varma Bairraju ,  Georgy Zorik Machulsky ,  Said Bshara

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45575

Abstract: An Application Programming Interface (API) allows a launching of a virtual machine where a queue count can be configured by a user. More specifically, each virtual machine can be assigned a pool of queues. Additionally, each virtual machine can have multiple virtual networking interfaces and a user can assign a number of queues from the pool to each virtual networking interface. Thus, a new metadata field is described that can be used with requests to launch a virtual machine. The metadata field includes one or more parameters that associate a number of queues with each virtual networking interface. A queue count can be dynamically configured by a user to ensure that the queues are efficiently used given that the user understands the intended application of the virtual machine being launched.

公开(公告)号：US11467998B1

公开(公告)日：2022-10-11

申请号：US17203231

申请日：2021-03-16

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Said Bshara ,  Jonathan Cohen ,  Avigdor Segal

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78 ,  G06F9/46

Abstract: Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

公开(公告)号：US10521377B1

公开(公告)日：2019-12-31

申请号：US16197289

申请日：2018-11-20

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Said Bshara ,  Evgeny Schmeilin

IPC: G06F13/28 ,  G06F13/42

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

公开(公告)号：US10061700B1

公开(公告)日：2018-08-28

申请号：US15230230

申请日：2016-08-05

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0855

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US20170270064A1

公开(公告)日：2017-09-21

申请号：US15616832

申请日：2017-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

Abstract: An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

公开(公告)号：US12093706B2

公开(公告)日：2024-09-17

申请号：US18186748

申请日：2023-03-20

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.