公开(公告)号：US12050545B2

公开(公告)日：2024-07-30

申请号：US17920961

申请日：2021-03-15

Applicant: CAMBRICON (XI'AN) SEMICONDUCTOR CO., LTD.

Inventor： Lu Chao ,  Fan Liang ,  Qinglong Chai ,  Xiao Zhang ,  Yanqiang Gao ,  Yongzhe Sun ,  Zhiyong Li ,  Chen Zhang ,  Tian Meng

IPC: G06F15/177 ,  G06F15/173

CPC classification number: G06F15/17306 ,  G06F15/17375 ,  G06F15/177

Abstract: A communication configuration apparatus for constructing a communication topology structure based on a plurality of processing nodes may be included in a combined processing apparatus. The combined processing apparatus further includes an interconnection interface and other processing apparatus. The communication configuration apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the communication configuration apparatus and other processing apparatuses, respectively. The storage apparatus is used for storing data of the communication configuration apparatus and other processing apparatus. A technical solution of the present disclosure may improve efficiency of inter-chip communication.

公开(公告)号：US20240054031A1

公开(公告)日：2024-02-15

申请号：US18491844

申请日：2023-10-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Kun Zheng

IPC: G06F9/54 ,  G06F15/173

CPC classification number: G06F9/546 ,  G06F15/17375

Abstract: In a data processing method in the field of artificial intelligence, a first processor of a data processing device sends a first search message to a second processor, and receives a second search message from a third processor. The first search message includes first data, and is for searching for an embedding parameter of the first data. The second search message includes second data and is for searching for an embedding parameter of the second data. The second processor and the third processor are respectively a next-hop processor and a previous-hop processor of the first processor in a ring communication architecture in which the first processor is located. The first, second, and third processors are among multiple processors in a data training system.

公开(公告)号：US20240045829A1

公开(公告)日：2024-02-08

申请号：US18131143

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Sriram Aananthakrishnan

IPC: G06F15/173

CPC classification number: G06F15/17375

Abstract: Techniques for multi-dimensional network sorted array merging. A first switch of a plurality of switches of an apparatus may receive a first element of a first array and a first element of a second array. The first switch may determine that the first element of the first array is less than the first element of the second array. The first switch may cause the first element of the first array to be stored as a first element of an output array.

公开(公告)号：US11836220B2

公开(公告)日：2023-12-05

申请号：US18176765

申请日：2023-03-01

Applicant: International Business Machines Corporation

Inventor： Xiaodong Cui ,  Wei Zhang ,  Mingrui Liu ,  Abdullah Kayi ,  Youssef Mroueh ,  Alper Buyuktosunoglu

IPC: G06F18/214 ,  G06F15/173 ,  G06N20/00 ,  G06N3/08 ,  G06F18/20

CPC classification number: G06F18/214 ,  G06F15/17375 ,  G06F18/285 ,  G06N3/08 ,  G06N20/00

Abstract: Systems, computer-implemented methods, and computer program products to facilitate updating, such as averaging and/or training, of one or more statistical sets are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include a computing component that averages a statistical set, provided by the system, with an additional statistical set, that is compatible with the statistical set, to compute an averaged statistical set, where the additional statistical set is obtained from a selected additional system of a plurality of additional systems. The computer executable components also can include a selecting component that selects the selected additional system according to a randomization pattern.

公开(公告)号：US20230350828A1

公开(公告)日：2023-11-02

申请号：US18309192

申请日：2023-04-28

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US11645225B2

公开(公告)日：2023-05-09

申请号：US17818855

申请日：2022-08-10

Applicant: Graphcore Limited

Inventor： Simon Knowles

IPC: G06F15/173 ,  G06N20/00 ,  G06K9/62

CPC classification number: G06F15/17375 ,  G06F15/17318 ,  G06K9/6256 ,  G06N20/00

Abstract: A computer, including a plurality of processing nodes arranged in two-dimensional arrays in respective front and rear layers. Each processing node has a set of activatable links. When activated, transmission of data items between the nodes connected via the activated link is enabled. When not activated, transmission of data items between the nodes is prevented. The set of activatable links including a respective link which connects the processing node to each adjacent node in the array, and to a facing processing node in the other layer. An allocation engine is configured to receive an allocation instruction and connected to the processing nodes to selectively activate the links in a configuration.

公开(公告)号：US10062422B2

公开(公告)日：2018-08-28

申请号：US15359895

申请日：2016-11-23

Applicant: Sonics, Inc.

Inventor： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC: G11C7/10 ,  G06F12/06 ,  G06F15/173

CPC classification number: G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

Abstract: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

公开(公告)号：US20170317679A1

公开(公告)日：2017-11-02

申请号：US15520294

申请日：2015-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwan SUH ,  Ki-seok KWON ,  Young-hwan PARK ,  Seung-won LEE ,  Suk-jin KIM

IPC: H03K19/177 ,  G06F15/173 ,  G06F15/76

CPC classification number: H03K19/17752 ,  G06F15/17375 ,  G06F15/7871 ,  G06F2015/768

Abstract: Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.

公开(公告)号：US09697122B2

公开(公告)日：2017-07-04

申请号：US14643375

申请日：2015-03-10

Applicant: DENSO CORPORATION

Inventor： Tomoyoshi Funazaki ,  Hirofumi Yamamoto

IPC: G06F12/08 ,  G06F12/0813 ,  G06F15/173

CPC classification number: G06F12/0813 ,  G06F15/17375 ,  G06F2212/154

Abstract: A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point. External and process completion events are input into the controller for generating a task start event toward the processing element according to the external and process completion events. Each access point has an access table storing a data write history when the processing element writes data in the memory in a memory access process. The processing element executes an event access process indicative of memory access process completion after the processing element completes the memory access process to the memory via the access point. The access point executes another event access process for inputting the process completion event into the controller of another stage, based on the data write history when the processing element executes the event access process.

公开(公告)号：US09304896B2

公开(公告)日：2016-04-05

申请号：US13959428

申请日：2013-08-05

Applicant: III Holdings 2, LLC

Inventor： Prashant R. Chandra ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Niall Joseph Dalton

IPC: G06F12/00 ,  G06F15/173 ,  G06F12/02

CPC classification number: G06F12/00 ,  G06F9/54 ,  G06F12/0223 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/17375 ,  G11C7/1036 ,  G11C7/1072 ,  G11C21/00 ,  Y02D10/14

Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.

Abstract translation: 数据处理节点具有节点间消息传递模块，其包括多个寄存器组，每组寄存器定义GET / PUT上下文的实例和多个数据处理核心，每个数据处理核心耦合到节点间消息传递模块。 每个数据处理核心包括映射功能，用于将多个用户级过程中的每一个映射到寄存器组中的不同的一个，从而映射到相应的GET / PUT上下文实例。 将每个用户级进程映射到不同的一组寄存器使得特定的一个用户级进程能够利用其相应的GET / PUT上下文实例来执行GET / PUT动作到不同的环形缓冲区 数据处理节点通过结构耦合到数据处理节点，而不涉及任何一个数据处理核心的操作系统。