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    Cache memory that supports tagless addressing
    1.
    发明授权
    Cache memory that supports tagless addressing 有权

    公开(公告)号：US12124382B2

    公开(公告)日：2024-10-22

    申请号：US17992443

    申请日：2022-11-22

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Trung A. Diep

    IPC: G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

    CPC classification number: G06F12/1063 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054

    Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

    System for Memory Resident Data Movement Offload and Associated Methods
    3.
    发明公开
    System for Memory Resident Data Movement Offload and Associated Methods 审中-公开

    公开(公告)号：US20240289281A1

    公开(公告)日：2024-08-29

    申请号：US18115607

    申请日：2023-02-28

    Applicant: IntelliProp, Inc.

    Inventor： Erich Hanke ,  Tracy Robert Spitler ,  James Milton Hull

    IPC: G06F12/1045 ,  G06F12/0882 ,  G06F13/16

    CPC classification number: G06F12/1063 ,  G06F12/0882 ,  G06F13/1642

    Abstract: A memory access engine is configured to receive a request comprising a command and to determine whether the command comprises an atomic command. If the command comprises the atomic command, the memory access engine determines whether the command includes a virtual address or a physical address. Based on determining that the command includes a virtual address, the memory access engine translates the virtual address to a corresponding physical address. The memory access engine determines an opcode included in the command and, based on the opcode, adds the command and the physical address to a particular queue of a plurality of queues. While a central processing unit (CPU) performs processing tasks, the memory access engine, based on the command, operates a memory fabric and, after receiving a message from the memory fabric indicating that the memory command has been completed, updates a status associated with the command to a completed status.

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