公开(公告)号：US20240273666A1

公开(公告)日：2024-08-15

申请号：US18450910

申请日：2023-08-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  David A. Gotwalt ,  Pratik Chandresh Shah ,  Jackson Dsouza ,  Subodh Asthana ,  Jairaj Dave ,  Piotr A. Dittrich ,  David E. Roberts

IPC: G06T1/20 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/485 ,  G06F9/4881

Abstract: Disclosed techniques relate to scheduling sets of graphics work using queues. In some embodiments, tracking circuitry implements entries for multiple tracking slots for a graphics processor. Queue access circuitry may access a data structure in memory that specifies multiple queues, where each queue enqueues control information for multiple sets of graphics work. Queue select circuitry may select sets of graphics work from the data structure based on one or more selection parameters and store control information for selected sets of graphics work in tracking slots of the tracking slot circuitry. Distribution circuitry may assign portions of respective sets of graphics work from the tracking slots to graphics processor circuitry for execution.

公开(公告)号：US20230367510A1

公开(公告)日：2023-11-16

申请号：US18318672

申请日：2023-05-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/1018 ,  G06F13/16 ,  G06F12/0871 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/0882 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230350828A1

公开(公告)日：2023-11-02

申请号：US18309192

申请日：2023-04-28

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US11693585B2

公开(公告)日：2023-07-04

申请号：US17353349

申请日：2021-06-21

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/1018 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US11567861B2

公开(公告)日：2023-01-31

申请号：US17519284

申请日：2021-11-04

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/1045

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US12175300B2

公开(公告)日：2024-12-24

申请号：US17399759

申请日：2021-08-11

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Steven Fishwick ,  Melissa L. Velez

IPC: G06F9/50 ,  G06F9/48

Abstract: Disclosed embodiments relate to software control of graphics hardware that supports logical slots. In some embodiments, a GPU includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine mappings between logical slots and distributed hardware slots for different sets of graphics work. Various mapping aspects may be software-controlled. For example, software may specify one or more of the following: priority information for a set of graphics work, to retain the mapping after completion of the work, a distribution rule, a target group of sub-units, a sub-unit mask, a scheduling policy, to reclaim hardware slots from another logical slot, etc. Software may also query status of the work.

公开(公告)号：US20240272961A1

公开(公告)日：2024-08-15

申请号：US18450952

申请日：2023-08-16

Applicant: Apple Inc.

Inventor： Steven Fishwick

IPC: G06F9/50 ,  G06T15/00

CPC classification number: G06F9/5077 ,  G06T15/005

Abstract: Disclosed techniques relate to assigning graphic work from logical slots of graphics control circuitry to distributed hardware slots of graphics processor sub-units. In some embodiments, control circuitry assigns respective portions of a set of graphics work from a logical slot to distributed hardware slots based on control information for the set of graphics work. When a full number of distributed hardware slots to be utilized by the set of graphics work are not available, control circuitry may assign a proper sub-set of portions of the set of graphics work to available distributed hardware slots. Control circuitry may support allocating any determined integer number of graphics processor sub-units in a range from one processor sub-unit to a total number of processor sub-units included in the apparatus.

公开(公告)号：US11714571B2

公开(公告)日：2023-08-01

申请号：US17353371

申请日：2021-06-21

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/1018 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230125798A1

公开(公告)日：2023-04-27

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/1018 ,  G06F13/16

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.