公开(公告)号：US12130744B2

公开(公告)日：2024-10-29

申请号：US17672116

申请日：2022-02-15

Applicant: Mobileye Vision Technologies Ltd.

Inventor： Yosef Kreinin ,  Yosi Arbeli ,  Gil Israel Dogon

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38 ,  G06F9/52 ,  G06F11/10 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F15/78 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811

CPC classification number: G06F12/0875 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3865 ,  G06F9/3891 ,  G06F9/526 ,  G06F11/1008 ,  G06F12/084 ,  G06F12/0842 ,  G06F15/7867 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811 ,  G06F2212/452 ,  G06F2212/62

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

公开(公告)号：US12130739B2

公开(公告)日：2024-10-29

申请号：US16833304

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F12/123 ,  G06F2212/1021

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20240354254A1

公开(公告)日：2024-10-24

申请号：US18759068

申请日：2024-06-28

Applicant: Lodestar Licensing Group LLC

Inventor： Richard C. Murphy

IPC: G06F12/0864 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0895 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C19/00

CPC classification number: G06F12/0864 ,  G06F9/30036 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0895 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/1012 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/6032 ,  G11C11/4094 ,  G11C19/00

Abstract: The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

公开(公告)号：US20240345990A1

公开(公告)日：2024-10-17

申请号：US18626775

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Varghese George ,  Ben Ashbaugh ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek Appu ,  Nicolas Galoppo Von Borries ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Nilay Mistry ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur Shah ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

公开(公告)号：US20240345956A1

公开(公告)日：2024-10-17

申请号：US18754499

申请日：2024-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20240345742A1

公开(公告)日：2024-10-17

申请号：US18629925

申请日：2024-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Seok KI ,  Chanik PARK ,  Sungwook RYU

IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/0811

CPC classification number: G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0811

Abstract: A persistent memory device is disclosed. The persistent memory device may include a cache coherent interconnect interface. The persistent memory device may include a volatile storage and a non-volatile storage. The volatile storage may include at least a first area and a second area. A backup power source may be configured to provide backup power selectively to the second area of the volatile storage. A controller may control the volatile storage and the non-volatile storage. The persistent memory device may use the backup power source while transferring a data from the second area of the volatile storage to the non-volatile storage based at least in part on a loss of a primary power for the persistent memory device.

公开(公告)号：US12118355B2

公开(公告)日：2024-10-15

申请号：US17506122

申请日：2021-10-20

Applicant: International Business Machines Corporation

Inventor： Shakti Kapoor ,  Manoj Dusanapudi ,  Nelson Wu

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0811

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0811

Abstract: Methods and systems for validating cache coherence in a data processing system are described. A processing element may detect a load instruction requesting the processing element to transfer data from a global memory location to a local memory location. The processing element may apply, in response to detecting the load instruction requesting the processing element to transfer data from the global memory location to the local memory location, a delay to the transfer of the data from the global memory location to the local memory location. The processing element may execute the load instruction and transferring the data from the global memory location to the local memory location with the applied delay. The processing element may validate, in response to executing the load instruction and transferring the data with the applied delay, a cache coherence of the data processing system.

公开(公告)号：US12111768B2

公开(公告)日：2024-10-08

申请号：US17427626

申请日：2020-02-13

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Amir Roozbeh ,  Alireza Farshin ,  Dejan Kostic ,  Gerald Q Maguire, Jr.

IPC: G06F12/00 ,  G06F9/455 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0871 ,  G06F12/0873

CPC classification number: G06F12/0871 ,  G06F9/45558 ,  G06F12/0646 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0873 ,  G06F2009/45583

Abstract: A method and device for controlling memory handling in a processing system comprising a cache shared between a plurality of processing units, wherein the cache comprises a plurality of cache portions. The method comprises obtaining first information pertaining to an allocation of a first memory portion of a memory to a first application, an allocation of a first processing unit of the plurality of processing units to the first application, and an association between a first cache portion of the plurality of cache portions and the first processing unit. The method further comprises reconfiguring a mapping configuration based on the obtained first information, and controlling a providing of first data associated with the first application to the first cache portion from the first memory portion using the reconfigured mapping configuration.

公开(公告)号：US20240320152A1

公开(公告)日：2024-09-26

申请号：US18607858

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM ,  Euiyeon WON ,  Donghyeon HAM ,  Youngsik EOM ,  Ara CHO

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.

公开(公告)号：US12099447B2

公开(公告)日：2024-09-24

申请号：US17965173

申请日：2022-10-13

Applicant: Arm Limited

Inventor： Alexander Alfred Hornung ,  Roberto Gattuso

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0871

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0871

Abstract: Prefetch circuitry generates, based on stream prefetch state information, prefetch requests for prefetching data to at least one cache. Cache control circuitry controls, based on cache policy information associated with cache entries in a given level of cache, at least one of cache entry replacement in the given level of cache, and allocation of data evicted from the given level of cache to a further level of cache. The stream prefetch state information specifies, for at least one stream of addresses, information representing an address access pattern for generating addresses to be specified by a corresponding series of prefetch requests. Cache policy information for at least one prefetched cache entry of the given level of cache (to which data is prefetched for a given stream of addresses) is set to a value dependent on at least one stream property associated with the given stream of addresses.