公开(公告)号：US20220197797A1

公开(公告)日：2022-06-23

申请号：US17130676

申请日：2020-12-22

申请人： Intel Corporation

发明人： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

IPC分类号： G06F12/0811 ,  G06F12/128 ,  G06F12/0815

摘要： An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US10175992B2

公开(公告)日：2019-01-08

申请号：US15283337

申请日：2016-10-01

申请人： Intel Corporation

发明人： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC分类号： G06F9/44 ,  G06F9/4401 ,  G06F12/126

摘要： Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

公开(公告)号：US20180285261A1

公开(公告)日：2018-10-04

申请号：US15476816

申请日：2017-03-31

申请人： Intel Corporation

发明人： Ayan Mandal ,  Eran Shifer ,  Leon Polishuk

IPC分类号： G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/1027 ,  G06F3/06

CPC分类号： G06F12/084 ,  G06F3/0653 ,  G06F9/5016 ,  G06F12/0223 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/604 ,  G06F2212/6046

摘要： Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

公开(公告)号：US20180121353A1

公开(公告)日：2018-05-03

申请号：US15335924

申请日：2016-10-27

申请人： Intel Corporation

发明人： Jayesh Gaur ,  Sreenivas Subramoney ,  Leon Polishuk

IPC分类号： G06F12/0804 ,  G06F12/0811

CPC分类号： G06F12/0831 ,  G06F12/12 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

摘要： Systems, methods, and processors to reduce redundant writes to memory. An embodiment of a system includes: a plurality of processors; a memory coupled to one of more of the plurality of processors; a cache coupled to the memory such that a dirty cache line evicted from the cache is written to the memory; and a redundant write detection circuitry coupled to the cache, wherein the redundant write detection circuitry to control write access to the cache based on a redundancy check of data to be written to the cache. The system may include a first predictor circuitry to deactivate the redundant write detection circuitry responsive to a determination that power consumed by the redundancy check is greater than the power it saves, or a second predictor circuitry to deactivate the redundant write detection circuitry when memory bandwidth saved from performing the redundancy check is not being utilized by memory reads.

公开(公告)号：US12130739B2

公开(公告)日：2024-10-29

申请号：US16833304

申请日：2020-03-27

申请人： Intel Corporation

发明人： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC分类号： G06F12/00 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/123

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/123 ,  G06F2212/1021

摘要： Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20230305960A1

公开(公告)日：2023-09-28

申请号：US17705015

申请日：2022-03-25

申请人： Intel Corporation

发明人： Leon Polishuk ,  Oz Shitrit ,  Elyada Bar-Chaim ,  Mauricio Valverde Monge ,  Ayan Mandal

IPC分类号： G06F12/0815

CPC分类号： G06F12/0815

摘要： Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

公开(公告)号：US20210303467A1

公开(公告)日：2021-09-30

申请号：US16833304

申请日：2020-03-27

申请人： Intel Corporation

发明人： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/123

摘要： Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20180173637A1

公开(公告)日：2018-06-21

申请号：US15387429

申请日：2016-12-21

申请人： Intel Corporation

发明人： Eran Shifer ,  Ravi K. Venkatesan ,  Leon Polishuk ,  Anant V. Nori ,  Ori Lempel ,  Manikantan R

IPC分类号： G06F12/0891 ,  G06F12/0815

CPC分类号： G06F12/0891 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/1024 ,  G06F2212/62

摘要： An indication of a first cache entry to be removed from a cache, the first cache entry corresponding to a first memory address in a memory may be received. A second memory address in the memory based at least in part on the first memory address may be identified. A request to identify a second cache entry in the cache corresponding to the second memory address and to determine whether a removal policy is satisfied may be sent. A response to the request, the response comprising an indication of the second cache entry to be removed from the cache based at least in part on the request may be sent. The first cache entry and the second cache entry from the cache may be removed. Data corresponding to the first and second cache entries to the memory with a single page file access may be written.

公开(公告)号：US12111762B2

公开(公告)日：2024-10-08

申请号：US17130676

申请日：2020-12-22

申请人： Intel Corporation

发明人： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

IPC分类号： G06F3/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F2212/1032

摘要： An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US20240220410A1

公开(公告)日：2024-07-04

申请号：US18089757

申请日：2022-12-28

申请人： Intel Corporation

发明人： Ayan Mandal ,  Prasanna Pandit ,  Neetu Jindal ,  Israel Diamand ,  Asaf Rubinstein ,  Leon Polishuk ,  Oz Shitrit

IPC分类号： G06F12/0806

CPC分类号： G06F12/0806 ,  G06F2212/62

摘要： Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.