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    DYNAMIC INCLUSIVE LAST LEVEL CACHE
    1.
    发明申请
    DYNAMIC INCLUSIVE LAST LEVEL CACHE 有权

    公开(公告)号：US20220197797A1

    公开(公告)日：2022-06-23

    申请号：US17130676

    申请日：2020-12-22

    申请人： Intel Corporation

    发明人： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

    IPC分类号： G06F12/0811 ,  G06F12/128 ,  G06F12/0815

    摘要： An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

    DEVICE, SYSTEM AND METHOD FOR PROVIDING A HIGH AFFINITY SNOOP FILTER
    2.
    发明公开
    DEVICE, SYSTEM AND METHOD FOR PROVIDING A HIGH AFFINITY SNOOP FILTER 审中-公开

    公开(公告)号：US20230305960A1

    公开(公告)日：2023-09-28

    申请号：US17705015

    申请日：2022-03-25

    申请人： Intel Corporation

    发明人： Leon Polishuk ,  Oz Shitrit ,  Elyada Bar-Chaim ,  Mauricio Valverde Monge ,  Ayan Mandal

    IPC分类号： G06F12/0815

    CPC分类号： G06F12/0815

    摘要： Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

    Shared read—using a request tracker as a temporary read cache
    5.
    发明授权
    Shared read—using a request tracker as a temporary read cache 有权

    公开(公告)号：US11422939B2

    公开(公告)日：2022-08-23

    申请号：US16727657

    申请日：2019-12-26

    申请人： Intel Corporation

    发明人： Israel Diamand ,  Ravi K. Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Michael Behar ,  Roni Rosner

    IPC分类号： G06F12/00 ,  G06F12/084 ,  G06F12/126

    摘要： Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.