公开(公告)号：US20240296114A1

公开(公告)日：2024-09-05

申请号：US18585643

申请日：2024-02-23

申请人： CANON KABUSHIKI KAISHA

发明人： WATARU OCHIAI

IPC分类号： G06F12/02

CPC分类号： G06F12/0223

摘要： A memory controller comprises a holding unit that holds a plurality of memory accesses to a memory that operates with a first clock. The memory controller generates a plurality of command requests for causing the memory to operate based on the plurality of memory accesses; determines, in synchronization with a second clock having a lower frequency than the first clock, whether a plurality of commands corresponding to the plurality of command requests are issuable, based on a constraint on issuance timings that are respectively set for the plurality of commands; selects, in synchronization with the second clock, one command to be issued to the memory from among commands that have been determined by the determining unit to be issuable; and outputs the selected one command to the memory in synchronization with the first clock.

公开(公告)号：US20240289266A1

公开(公告)日：2024-08-29

申请号：US18441775

申请日：2024-02-14

申请人： Micron Technology, Inc.

发明人： Sujeet Ayyapureddi

IPC分类号： G06F12/02

CPC分类号： G06F12/0223

摘要： Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.

公开(公告)号：US20240272984A1

公开(公告)日：2024-08-15

申请号：US18431232

申请日：2024-02-02

申请人： Micron Technology, Inc.

发明人： Sujeet Ayyapureddi

IPC分类号： G06F11/10 ,  G06F12/02

CPC分类号： G06F11/1076 ,  G06F12/0223

摘要： A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

公开(公告)号：US20240265004A1

公开(公告)日：2024-08-08

申请号：US18442653

申请日：2024-02-15

申请人： Chia Network Inc.

发明人： Bram Cohen ,  Krzysztof Pietrzak ,  Mariano Sorgente

IPC分类号： G06F16/23 ,  G06F12/02 ,  H04L9/00 ,  H04L9/32

CPC分类号： G06F16/2379 ,  G06F12/0223 ,  H04L9/3239 ,  G06F2212/1048 ,  H04L9/50

摘要： A method for extending a blockchain comprises, at a space server: allocating an amount of drive storage for generating proofs-of-space; or accessing a first challenge based on a prior block of the blockchain, the prior block comprising a first proof-of-space and a first proof-of-time; in response to accessing the first challenge, generating a second proof-of-space based on the first challenge and the amount of drive storage, the second proof-of-space indicating allocation of the amount of drive storage; accessing a second proof-of-time based on the prior block and indicating a first time delay elapsed after extension of the blockchain with the prior block; generating a new block comprising the second proof-of-space and the second proof-of-time; and broadcasting the new block over a distributed network.

公开(公告)号：US20240257860A1

公开(公告)日：2024-08-01

申请号：US18566558

申请日：2022-05-31

申请人： Rambus Inc.

发明人： Thomas Vogelsang ,  Brent Steven Haukness ,  Gary Bela Bronner

IPC分类号： G11C11/4074 ,  G06F12/02 ,  G11C11/408 ,  G11C11/4091

CPC分类号： G11C11/4074 ,  G06F12/0223 ,  G11C11/4085 ,  G11C11/4091

摘要： A dynamic random access memory (DRAM) device includes memory core circuitry and power supply circuitry. The memory core circuitry includes an array of DRAM storage cells, with ones of the DRAM storage cells coupled to wordline and bitline power supply busses. The power supply circuitry is coupled to the wordline and bitline power supply busses. The power supply circuitry is responsive to a control signal to generate one of a first set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a first normal mode of operation, or to generate a second set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a second normal mode of operation. A value of the control signal is based on a temperature parameter associated with the DRAM device.

公开(公告)号：US20240233798A9

公开(公告)日：2024-07-11

申请号：US18327335

申请日：2023-06-01

申请人： Samsung Electronics Co., Ltd.

发明人： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

IPC分类号： G11C11/406 ,  G06F12/02

CPC分类号： G11C11/406 ,  G06F12/0223

摘要： A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US12008351B2

公开(公告)日：2024-06-11

申请号：US17980437

申请日：2022-11-03

申请人： Oracle International Corporation

发明人： Maurizio Cimadamore ,  James Malcolm Laskey ,  Jorn Bender Vernee ,  Vladimir Vitalyevich Ivanov

IPC分类号： G06F8/41 ,  G06F9/445 ,  G06F12/02

CPC分类号： G06F8/44 ,  G06F9/44557 ,  G06F12/0223 ,  G06F8/443 ,  G06F2212/7202

摘要： Techniques for representing a native function using an executable reference are disclosed. The system receives an instruction to create an executable reference for a native function, including a method type comprising a method signature corresponding to the executable reference, and a function description including (a) a memory layout corresponding to data returned by the function and (b) memory layouts corresponding to parameters required by the function. The system selects an application binary interface (ABI). The system generates code that, for each parameter, of the one or more parameters required by the function, converts the parameter from a value formatted for use by a Java Virtual machine to a value formatted for use in the native function, based on the selected ABI. Responsive to invocation of the executable reference, the generated code and the native function may be executed.

公开(公告)号：US20240135980A1

公开(公告)日：2024-04-25

申请号：US18327335

申请日：2023-05-31

申请人： Samsung Electronics Co., Ltd.

发明人： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

IPC分类号： G11C11/406 ,  G06F12/02

CPC分类号： G11C11/406 ,  G06F12/0223

摘要： A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20240126680A1

公开(公告)日：2024-04-18

申请号：US18391714

申请日：2023-12-21

申请人： David KEPPEL ,  David OZOG ,  Lawrence STEWART ,  Sri Raj PAUL ,  Md RAHMAN

发明人： David KEPPEL ,  David OZOG ,  Lawrence STEWART ,  Sri Raj PAUL ,  Md RAHMAN

IPC分类号： G06F12/02

CPC分类号： G06F12/0223

摘要： Various examples relate to apparatuses, devices, methods and computer programs for allocating memory. An apparatus comprises interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to process instructions of a software application of a local processing element participating in a partitioned global address space, allocate, upon processing an instruction for allocating memory on a symmetric heap being used across a plurality of processing elements participating in the partitioned global address space, memory on the symmetric heap, wherein, if the instruction for allocating memory indicates that memory is to be allocated with a variable size, the memory allocated on the symmetric heap has a size that is specific for the local processing element.

公开(公告)号：US20240111758A1

公开(公告)日：2024-04-04

申请号：US18537268

申请日：2023-12-12

申请人： Charles Schwab & Co., Inc.

发明人： Eric TESSE

IPC分类号： G06F16/23 ,  G06F12/02 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/903 ,  H04L69/324

CPC分类号： G06F16/2379 ,  G06F12/0223 ,  G06F16/2255 ,  G06F16/2264 ,  G06F16/2358 ,  G06F16/24562 ,  G06F16/90344 ,  H04L69/324 ,  G06F2212/1041

摘要： A computationally-efficient system for encoding a message object implements instructions including determining a token of the message object. The token identifies a structure of the message object. The instructions include obtaining a dictionary definition based on the token. The dictionary definition describes the structure of the message. The message includes multiple entries. Each of the entries is characterized by a data type and a field identifier. The dictionary definition defines an order of the entries. The instructions include, according to an order specified by the dictionary definition, selecting each entry of a set of entries in the message in sequence and writing the entry to a byte queue exclusive of the data type and the field identifier. The instructions include initiating transmission of the byte queue over a communications network.