公开(公告)号：US20240361823A1

公开(公告)日：2024-10-31

申请号：US18764639

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok OH

IPC: G06F1/3234 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F1/3275 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

公开(公告)号：US12125517B2

公开(公告)日：2024-10-22

申请号：US17804414

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20240331763A1

公开(公告)日：2024-10-03

申请号：US18591798

申请日：2024-02-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TAKAMASA SUZUKI ,  NOBUO YAMAMOTO ,  IZUMI NAKAI

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

Abstract: Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.

公开(公告)号：US20240330178A1

公开(公告)日：2024-10-03

申请号：US18738851

申请日：2024-06-10

Applicant: The Trustees of Princeton University

Inventor： Naveen VERMA ,  Hossein VALAVI ,  Hongyang JIA

IPC: G06F12/06 ,  G06F12/02 ,  G06F17/16 ,  G06N3/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20

CPC classification number: G06F12/0607 ,  G06F12/0207 ,  G06F17/16 ,  G06N3/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20 ,  G06F2212/454

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

公开(公告)号：US20240312518A1

公开(公告)日：2024-09-19

申请号：US18586149

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/50

CPC classification number: G11C11/5642 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/5628 ,  G11C29/50004

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US20240312513A1

公开(公告)日：2024-09-19

申请号：US18600715

申请日：2024-03-10

Applicant: Kioxia Corporation

Inventor： Tomohiko ITO ,  Hiroshi YOSHIHARA

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4085

Abstract: According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor; a second memory string including a second memory cell transistor; a first word line commonly coupled to a gate of each of the first memory cell transistor and the second memory cell transistor; and a control circuit, wherein during a first read operation of reading data from the first memory string, a threshold voltage of the first memory cell transistor is less than a first voltage, a threshold voltage of the second memory cell transistor is equal to or greater than the first voltage, and the control circuit is configured to supply a voltage equal to or less than the first voltage to the first word line.

公开(公告)号：US12094517B2

公开(公告)日：2024-09-17

申请号：US17994397

申请日：2022-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Shuo Hsu

IPC: G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G11C11/4085

Abstract: A word line pump device of a dynamic random access memory (DRAM) chip and a clamp circuit thereof are provided. The DRAM chip receives a first voltage and a second voltage from outside, and the first voltage is smaller than the second voltage. The clamp circuit clamps a word line voltage to the second voltage in response to the word line pump device not receiving a power supply voltage.

公开(公告)号：US12093110B2

公开(公告)日：2024-09-17

申请号：US17940769

申请日：2022-09-08

Applicant: Changxin Memory Technologies, Inc.

Inventor： Weibing Shang ,  Enpeng Gao

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/148 ,  G11C11/4074

Abstract: The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

公开(公告)号：US20240304233A1

公开(公告)日：2024-09-12

申请号：US18667802

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Jin Seung Son ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuity to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.

公开(公告)号：US12079022B2

公开(公告)日：2024-09-03

申请号：US18493796

申请日：2023-10-24

Applicant: Apple Inc.

Inventor： Seyedeh Sedigheh Hashemi ,  Vahid Majidzadeh Bafar ,  Ali Mesgarani ,  Mansour Keramat

IPC: G05F3/26 ,  G05F3/20 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G05F3/26 ,  G05F3/205 ,  G11C5/147 ,  G11C11/4074

Abstract: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.