公开(公告)号：US20240347120A1

公开(公告)日：2024-10-17

申请号：US18362804

申请日：2023-07-31

Applicant: SanDisk Technologies LLC

Inventor： SHIV HARIT MATHUR ,  Sai Ravi Teja KONAKALLA ,  Niravkumar Natwarbhai PATEL ,  Utkarsh SRIVASTAVA ,  Gopikrishna SIDDULA

IPC: G11C29/02 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C29/021 ,  G11C5/147 ,  G11C7/1096 ,  G11C29/022

Abstract: Embodiments of the present technology provide memory cards intelligently designed to provide protection when mistakenly inserted into non-memory card hosts. Embodiments achieve such protection with less footprint/circuitry than existing fail-safe solutions, and without electrical overstress-causing offset voltages characteristic of existing fail-safe solutions. To realize these advantages, a memory card of the present technology includes a fail-safe reference voltage supply circuit that operates in a “fail-safe mode” by default, and exits and re-enters the fail-safe mode in response to voltage mode driver output enable (OE) signals.

公开(公告)号：US20240312494A1

公开(公告)日：2024-09-19

申请号：US18675997

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

公开(公告)号：US12094558B2

公开(公告)日：2024-09-17

申请号：US18318264

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Meng-Sheng Chang ,  Tung-Cheng Chang ,  Yih Wang

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C5/147 ,  G11C7/1084 ,  G11C17/165 ,  G11C17/18

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

公开(公告)号：US12079022B2

公开(公告)日：2024-09-03

申请号：US18493796

申请日：2023-10-24

Applicant: Apple Inc.

Inventor： Seyedeh Sedigheh Hashemi ,  Vahid Majidzadeh Bafar ,  Ali Mesgarani ,  Mansour Keramat

IPC: G05F3/26 ,  G05F3/20 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G05F3/26 ,  G05F3/205 ,  G11C5/147 ,  G11C11/4074

Abstract: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.

公开(公告)号：US20240290376A1

公开(公告)日：2024-08-29

申请号：US18506202

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Wenlun Zhang ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Yuan He

IPC: G11C11/4091 ,  G11C5/14 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4096

Abstract: Sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. Additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. Moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.

公开(公告)号：US20240286402A1

公开(公告)日：2024-08-29

申请号：US18572767

申请日：2021-07-06

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Eric Thomas Martin ,  James Michael Gardner ,  Rogelio Cicili

IPC: B41J2/045 ,  G11C5/14

CPC classification number: B41J2/04548 ,  G11C5/147

Abstract: An integrated circuit includes a plurality of fluid actuation devices, a plurality of memory cells, a high-voltage high-power supply node, and a high-voltage low-power supply node. The high-voltage high-power supply node is to supply a first voltage and a first maximum current to the plurality of fluid actuation devices. The high-voltage low-power supply node is to supply a second voltage and a second maximum current to the plurality of memory cells.

公开(公告)号：US20240282356A1

公开(公告)日：2024-08-22

申请号：US18171024

申请日：2023-02-17

Applicant: Winbond Electronics Corp.

Inventor： Takahiko SATO

IPC: G11C11/4074 ,  G11C5/14

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C5/148

Abstract: A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

公开(公告)号：US12066849B2

公开(公告)日：2024-08-20

申请号：US17744067

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Jun Roh ,  Jae Woo Park ,  Jun Han Choi ,  Myoung Bo Kwak ,  Jung Hwan Choi

IPC: G05F1/56 ,  G11C5/14 ,  G11C7/10 ,  H03F3/45

CPC classification number: G05F1/56 ,  G11C5/147 ,  G11C7/10 ,  H03F3/45071

Abstract: A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

公开(公告)号：US20240265951A1

公开(公告)日：2024-08-08

申请号：US18137370

申请日：2023-04-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hoa Vu ,  Stephen Trinh ,  Stanley Hong ,  Thuan Vu ,  Nghia Le ,  Duc Nguyen ,  Hien Pham

IPC: G11C5/14 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C13/004

Abstract: In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.

公开(公告)号：US20240242742A1

公开(公告)日：2024-07-18

申请号：US18204806

申请日：2023-06-01

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: Data storage systems and semiconductor devices are disclosed. In an embodiment, a storage system includes a circuit board, a semiconductor device coupled to the circuit board and including at least one memory and a controller, wherein the controller is in communication with the at least one memory and configured to control the at least one memory, and a voltage level regulator coupled to the circuit board and including at least one switching element and located outside the at least one memory and the controller in the semiconductor device, the voltage level regulator configured to output, to at least one of the at least one memory or the controller, a driving voltage obtained by adjusting a level of at least one external voltage received from a device outside the semiconductor device.