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公开(公告)号：US11966247B1
公开(公告)日：2024-04-23
申请号：US18160536
申请日：2023-01-27
Applicant: pSemi Corporation
Inventor： Rogelio Cicili
Abstract: Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.
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公开(公告)号：US11934609B2
公开(公告)日：2024-03-19
申请号：US17301080
申请日：2021-03-24
Applicant: Microchip Technology Incorporated
Inventor： Lei Zou
CPC classification number: G06F3/04166 , G05F3/205 , G05F3/262
Abstract: One or more embodiments relate to a multi-bias mode current conveyor. Such a current conveyor may include an input terminal, a reference terminal, an output terminal, a first and second cascoded current mirrors, and a biasing circuit. The first cascoded current mirror and a second cascoded current mirror may be arranged as a current conveyor that is configured to provide an output current that a mirror of an input current. The biasing circuit may be configured to provide a bias voltage selectively exhibiting a first voltage level or a second voltage level. The bias voltage may be provided at least partially responsive to a state of the input current. The biasing circuit may be arranged to apply the bias voltage to at least one of the first cascoded current mirror or the second cascoded current mirror.
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3.发明授权公开(公告)号：US11791834B2
公开(公告)日：2023-10-17
申请号：US17672378
申请日：2022-02-15
Inventor： Yu-Jie Huang , Mu-Shan Lin , Chien-Chun Tsai
Abstract: A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.
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公开(公告)号：US20230283243A1
公开(公告)日：2023-09-07
申请号：US18172008
申请日：2023-02-21
Applicant: Infineon Technologies AG
Inventor： Herwig Wappis , Peter Singerl , Martin Mataln , Gerhard Maderbacher
CPC classification number: H03F1/302 , G05F3/205 , H03F1/0266
Abstract: A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.
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公开(公告)号：US20190187737A1
公开(公告)日：2019-06-20
申请号：US16173576
申请日：2018-10-29
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Masaharu MATSUDAIRA , Takashi HASE , Akira TANABE , Kazuya UEJIMA
CPC classification number: G05F3/205 , G01K7/01 , G05F3/245 , H03K17/145 , H03K2217/0018
Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.
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Patent Agency Ranking
公开(公告)号：US10061339B1
公开(公告)日：2018-08-28
申请号：US15802965
申请日：2017-11-03
Applicant: NXP USA, Inc.
Inventor： Andre Luis Vilas Boas , Richard Titov Lara Saez , Ivan Carlos Ribeiro Do Nascimento , Marcelo de Paula Campos , Pedro Barbosa Zanetta
CPC classification number: G05F3/26 , G05F3/205 , G11C5/145 , G11C5/146 , H02M1/083 , H02M3/07 , H03F3/45475 , H03F2200/78
Abstract: A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.
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公开(公告)号：US10044260B2
公开(公告)日：2018-08-07
申请号：US15665493
申请日：2017-08-01
Applicant: Sk hynix Inc.
Inventor： Chung-Hun Jeon
CPC classification number: H02M3/073 , G05F3/205 , G11C5/146 , H03K17/063 , H03K2217/0018
Abstract: A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.
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公开(公告)号：US20180183328A1
公开(公告)日：2018-06-28
申请号：US15665493
申请日：2017-08-01
Applicant: SK hynix Inc.
Inventor： Chung-Hun JEON
CPC classification number: H02M3/073 , G05F3/205 , G11C5/146 , H03K17/063 , H03K2217/0018
Abstract: A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.
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公开(公告)号：US10003325B2
公开(公告)日：2018-06-19
申请号：US15281064
申请日：2016-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sumeer Goel , Kenneth Hicks , Jan-Michael Huber , Rajesh Kapaluru , Prashant Kenkare
IPC: H03K3/00 , H03K3/012 , H03K17/687 , G05F3/20
CPC classification number: H03K3/012 , G05F3/205 , H03K17/6872 , H03K19/0016 , H03K2217/0018
Abstract: According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.
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公开(公告)号：US20180059703A1
公开(公告)日：2018-03-01
申请号：US15805904
申请日：2017-11-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jerry L. Doorenbos
Abstract: One example includes a reference voltage generator system. The system includes an amplifier configured to generate a reference voltage based on a respective input voltage provided at each of at least one input of the amplifier. The system also includes at least one input transistor that is coupled to the at least one input of the amplifier and is statically-biased to conduct a current to set an amplitude of the respective input voltage provided at each of the at least one input of the amplifier. Each of the at least one input transistor includes an input terminal that is coupled in series with an input resistor.
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