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公开(公告)号：US11979151B2
公开(公告)日：2024-05-07
申请号：US17933634
申请日：2022-09-20
申请人： NXP USA, Inc.
IPC分类号： H03K17/693 , H03K17/081 , H03K19/173 , H03K19/17784 , H03M1/12
CPC分类号： H03K19/1737 , H03K17/08104 , H03K19/17784 , H03M1/1205
摘要： An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.
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公开(公告)号：US10734975B1
公开(公告)日：2020-08-04
申请号：US16406256
申请日：2019-05-08
申请人： NXP USA, Inc.
摘要： A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.
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公开(公告)号：US10061339B1
公开(公告)日：2018-08-28
申请号：US15802965
申请日：2017-11-03
申请人： NXP USA, Inc.
发明人： Andre Luis Vilas Boas , Richard Titov Lara Saez , Ivan Carlos Ribeiro Do Nascimento , Marcelo de Paula Campos , Pedro Barbosa Zanetta
CPC分类号： G05F3/26 , G05F3/205 , G11C5/145 , G11C5/146 , H02M1/083 , H02M3/07 , H03F3/45475 , H03F2200/78
摘要： A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.
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公开(公告)号：US09984763B1
公开(公告)日：2018-05-29
申请号：US15365041
申请日：2016-11-30
申请人： NXP USA, INC.
发明人： Andre Luis Vilas Boas , Richard Titov Lara Saez , Ivan Carlos Ribeiro Do Nascimento , Javier Mauricio Olarte Gonzalez
CPC分类号： G11C27/024 , H03K5/159
摘要： A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.
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公开(公告)号：US09964975B1
公开(公告)日：2018-05-08
申请号：US15720318
申请日：2017-09-29
申请人： NXP USA, Inc.
摘要： A circuit includes a first resistive element having a first terminal coupled to an input node to receive a negative voltage, a second resistive element having a first terminal coupled to a first power supply terminal, and a third resistive element having a first terminal coupled to the first power supply terminal. A first current mirror includes a first transistor coupled to a second terminal of the second resistive element and a second transistor coupled to a second terminal of the third resistive element and the first transistor, wherein the output node corresponds to the second terminal of the third resistive element. A second current mirror includes a third transistor coupled to the first transistor and a fourth transistor coupled to the second transistor, third transistor, and a second terminal of the first resistive element. The circuit converts the negative voltage to the positive proportion voltage.
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公开(公告)号：US10243456B2
公开(公告)日：2019-03-26
申请号：US15611961
申请日：2017-06-02
申请人： NXP USA, INC.
摘要： A voltage regulator includes first and second bias circuits, a transistor, and a load prediction circuit. The transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode for providing a regulated output voltage, and a control electrode. The first biasing circuit is for providing a first bias voltage to the control electrode of the transistor in response to a feedback signal generated from the regulated output voltage. The second biasing circuit is for providing a second bias voltage to the control electrode of the transistor in response to a control signal. The load current prediction circuit is coupled to the second biasing circuit. The load prediction circuit is for providing the control signal to the second biasing circuit in response to determining that a load current at the second current electrode is expected to increase.
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公开(公告)号：US20240097686A1
公开(公告)日：2024-03-21
申请号：US17933634
申请日：2022-09-20
申请人： NXP USA, Inc.
IPC分类号： H03K19/173 , H03K17/081 , H03K19/17784 , H03M1/12
CPC分类号： H03K19/1737 , H03K17/08104 , H03K19/17784 , H03M1/1205
摘要： An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.
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公开(公告)号：US11106231B1
公开(公告)日：2021-08-31
申请号：US17038134
申请日：2020-09-30
申请人： NXP USA, Inc.
摘要： An integrated circuit (IC) is disclosed that includes a load circuit, and a voltage regulator circuit configured to provide a load voltage and a load current to the load circuit. The voltage regulator circuit can regulate the load voltage based on the load current.
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9.发明授权公开(公告)号：US11171562B1
公开(公告)日：2021-11-09
申请号：US16922926
申请日：2020-07-07
申请人： NXP USA, Inc.
摘要： Multi-sense point voltage regulator systems are provided for usage in conjunction with power-regulated devices, such as system-on-chip and microcontroller unit devices. In embodiments, the multi-sense point voltage regulator system includes a multiplexer selector circuit and a voltage regulator. The multiplexer selector circuit is configured to: (i) monitor a local voltages at multiple sense points within an integrated circuit (IC) die circuit structure; and (ii) generate a feedback voltage indicative of a lowest one of the monitored local voltages. The voltage regulator is configured to generate a regulated power supply output voltage as a function of a differential between the feedback voltage and the reference voltage, with the regulated power supply output voltage provided to the IC die circuit structure to drive operation thereof.
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公开(公告)号：US10979033B2
公开(公告)日：2021-04-13
申请号：US16939226
申请日：2020-07-27
申请人： NXP USA, Inc.
摘要： A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.
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