公开(公告)号：US20190007035A1

公开(公告)日：2019-01-03

申请号：US15847539

申请日：2017-12-19

申请人： SK hynix Inc.

发明人： Jae-Heung KIM

IPC分类号： H03K5/159

CPC分类号： H03K5/159 ,  H03K5/133

摘要： A delay cell may include: a first inverter coupled to an input terminal; a second inverter coupled between the first inverter and an output terminal; an additional inverter coupled in parallel to the first inverter; and a delay element suitable for selectively coupling the additional inverter to the input terminal under control of a control signal.

公开(公告)号：US20180226965A1

公开(公告)日：2018-08-09

申请号：US15725593

申请日：2017-10-05

申请人： SK hynix Inc.

发明人： Kyu Dong HWANG

IPC分类号： H03K17/284 ,  H03K5/159 ,  H03K21/02

CPC分类号： H03K17/284 ,  H03K5/159 ,  H03K21/026 ,  H03K2005/00058

摘要： A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

公开(公告)号：US09998099B2

公开(公告)日：2018-06-12

申请号：US14384374

申请日：2014-05-23

申请人： QUALCOMM Incorporated

发明人： Wenjun Su ,  Chulkyu Lee ,  Le Zhang ,  Guangming Yin

IPC分类号： G05F1/00 ,  H02M3/07 ,  H03K5/159 ,  H03K3/011 ,  H03K17/14 ,  H03K19/003 ,  G05F3/26

CPC分类号： H03K3/011 ,  G05F1/00 ,  G05F3/205 ,  G05F3/242 ,  G05F3/262 ,  H02M3/07 ,  H03K5/159 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

公开(公告)号：US20180151242A1

公开(公告)日：2018-05-31

申请号：US15365041

申请日：2016-11-30

申请人： NXP USA, INC.

发明人： Andre Luis Vilas Boas ,  Richard Titov Lara Saez ,  Ivan Carlos Ribeiro Do Nascimento ,  Javier Mauricio Olarte Gonzalez

IPC分类号： G11C27/02 ,  H03K17/06 ,  H03K5/159

CPC分类号： G11C27/024 ,  H03K5/159

摘要： A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

公开(公告)号：US09935113B2

公开(公告)日：2018-04-03

申请号：US15604672

申请日：2017-05-25

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： H01L27/112 ,  H01L29/78 ,  H01L23/525 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/16 ,  H01L29/423 ,  G11C17/16 ,  G11C17/18

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/419 ,  G11C17/165 ,  G11C17/18 ,  G11C2207/002 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/7848 ,  H01L29/7851 ,  H02M2003/075 ,  H03K3/012 ,  H03K5/134 ,  H03K5/159 ,  H03K17/687 ,  H03K2005/00195

摘要： A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

公开(公告)号：US20180076798A1

公开(公告)日：2018-03-15

申请号：US15695333

申请日：2017-09-05

申请人： Fujitsu Limited

发明人： Kouichi Kanda

IPC分类号： H03K3/356 ,  H03K5/159

CPC分类号： H03K3/356104 ,  H03K3/356121 ,  H03K5/159

摘要： A flip-flop circuit includes a data capture circuit that captures data based on a clock, a data hold circuit that holds an output of the data capture circuit based on the clock, and a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock, when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit.

公开(公告)号：US20180054115A1

公开(公告)日：2018-02-22

申请号：US15444920

申请日：2017-02-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Taichi OGAWA ,  Takeshi Ueno ,  Tetsuro Itakura ,  Osamu Watanabe ,  Takayuki Miyazaki ,  Yosuke Toyama

IPC分类号： H02M3/04 ,  H03K5/159 ,  H03K3/037

CPC分类号： H02M3/04 ,  H02M3/1563 ,  H03K3/037 ,  H03K5/159 ,  H03K2005/00013

摘要： An electronic circuit according to one embodiment of the present invention includes a first logic circuit, a second logic circuit, first and second capacitors, and a connection circuit. The first logic circuit has a first output terminal from which a first output signal based on a first input signal is output. The second logic circuit outputs a second output signal obtained by inversion of the first output signal is output in a steady state. The first and second capacitors each have one terminal at a first voltage. The connection circuit connects one of the first output terminal and the second output terminal to the first capacitor, and the other to the second capacitor. The connection circuit interchanges connection destinations of the first capacitor and the second capacitor in accordance with a received first connection control signal.

公开(公告)号：US20170346464A1

公开(公告)日：2017-11-30

申请号：US15498525

申请日：2017-04-27

申请人： MEDIATEK Inc.

发明人： Keng-Meng Chang ,  Yao-Chi Wang

IPC分类号： H03H11/30 ,  H03K5/159 ,  H03K19/21

CPC分类号： H03H11/30 ,  H03K5/159 ,  H03K19/0005 ,  H03K19/017545 ,  H03K19/21 ,  H03L1/00 ,  H03L1/022 ,  H03L7/0816 ,  H03L7/103 ,  H03L7/113 ,  H03L7/18 ,  H04B1/0475 ,  H04B1/1638 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

摘要： A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

公开(公告)号：US20170324405A1

公开(公告)日：2017-11-09

申请号：US15361594

申请日：2016-11-28

申请人： STMicroelectronics (Rousset) SAS

发明人： Albert Martinez ,  Michel Agoyan

IPC分类号： H03K17/00 ,  H03K19/003 ,  H03K5/159

CPC分类号： H03K17/005 ,  G06F7/58 ,  H03K3/84 ,  H03K5/159 ,  H03K19/003 ,  H03K19/1737

摘要： A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US09729131B2

公开(公告)日：2017-08-08

申请号：US14866250

申请日：2015-09-25

申请人： Micron Technology, Inc.

发明人： Katsuhiro Kitagawa

IPC分类号： H03K5/156

CPC分类号： H03K5/1565 ,  H03K5/159

摘要： Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.