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    Semiconductor device having duty-cycle corrector
    1.
    发明授权
    Semiconductor device having duty-cycle corrector 有权

    公开(公告)号：US11843385B1

    公开(公告)日：2023-12-12

    申请号：US17857869

    申请日：2022-07-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuo Satoh

    IPC: H03K5/156 ,  H03K5/134 ,  G11C11/4076

    CPC classification number: H03K5/1565 ,  G11C11/4076 ,  H03K5/134

    Abstract: Disclosed herein is an apparatus that includes: a first input node supplied with a first clock signal; a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series; a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series; a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.

    DELAY CELL CIRCUITS
    2.
    发明公开
    DELAY CELL CIRCUITS 审中-公开

    公开(公告)号：US20230179184A1

    公开(公告)日：2023-06-08

    申请号：US17924315

    申请日：2021-05-11

    Applicant: Nordic Semiconductor ASA

    Inventor： Cole NIELSEN

    IPC: H03K3/03 ,  H03K5/134

    CPC classification number: H03K3/0322 ,  H03K5/134

    Abstract: A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

    PULSE WIDTH FILTERING CIRCUIT
    7.
    发明申请
    PULSE WIDTH FILTERING CIRCUIT 审中-公开

    公开(公告)号：US20180123576A1

    公开(公告)日：2018-05-03

    申请号：US15795366

    申请日：2017-10-27

    Applicant: Mosway Technologies Limited

    Inventor： On Bon Peter CHAN

    IPC: H03K5/156 ,  H03K5/1534 ,  H03K5/134

    CPC classification number: H03K5/1565 ,  H03K5/134 ,  H03K5/1534 ,  H03K17/005 ,  H03K19/20

    Abstract: A pulse width filtering circuit for filtering pulse signals includes an input transition detection circuit detecting change of state of an input signal, including a first transition from a low signal to a high signal and a second transition from the high signal to the low signal; a first delay circuit determining whether the high signal from the first transition is maintained longer than a first period and, if so, generating a first output indicative of the first transition, after the first period; a second delay circuit determining whether the low signal from the second transition is maintained for longer than a second period and, if so, generating a second output indicative of the second transition, after the second period; and a switching circuit connected to the first and second delay circuits and selectively outputting the first output and the second output, based on the state of the input signal.

    Dual-edge trigger clock gater
    9.
    发明授权
    Dual-edge trigger clock gater 有权

    公开(公告)号：US09660620B1

    公开(公告)日：2017-05-23

    申请号：US15217669

    申请日：2016-07-22

    Applicant: Apple Inc.

    Inventor： Victor Zyuban ,  Nimish Kabe

    IPC: H03K5/01 ,  G05B19/41 ,  H03K19/21 ,  H03K5/00

    CPC classification number: H03K5/01 ,  H03K5/134 ,  H03K19/0016 ,  H03K19/21 ,  H03K2005/00019 ,  H03K2005/00065 ,  H03K2005/00234

    Abstract: Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.

    SIGNAL DELAY CELLS
    10.
    发明申请
    SIGNAL DELAY CELLS 审中-公开
    信号延迟细胞

    公开(公告)号：US20170047917A1

    公开(公告)日：2017-02-16

    申请号：US15304491

    申请日：2014-04-16

    Applicant: WASHINGTON STATE UNIVERSITY

    Inventor： Deukhyoun HEO ,  Pawan AGARWAL

    IPC: H03K5/13 ,  H03L7/099 ,  H03K5/134

    CPC classification number: H03K5/131 ,  H03K5/134 ,  H03K2005/00058 ,  H03K2005/00071 ,  H03K2005/00195 ,  H03L7/0992

    Abstract: In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages.

    Abstract translation: 在一些示例中，描述了电路。 电路可以包括在数字锁相环（PLL）中，并且可以包括第一延迟单元，第二延迟单元和延迟控制器。 第一延迟单元可以包括第一反相器电路，其包括第一和第二晶体管，并且可以被配置为接收和延迟第一信号。 第一反相器电路的延迟可以基于分别提供给第一和第二晶体管的第一和第二电压。 第二延迟单元可以包括第二反相器电路，其包括第三和第四晶体管，并且可以被配置为接收和延迟第二信号。 第二逆变器电路的延迟可以基于分别提供给第三和第四晶体管的第三和第四电压。 延迟控制器可以被配置为提供第一，第二，第三和第四电压。

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