公开(公告)号：US20190181862A1

公开(公告)日：2019-06-13

申请号：US16202573

申请日：2018-11-28

Applicant: OVH

Inventor： Emmanuel Joseph Henri FLIPO ,  Christophe Maurice THIBAUT

IPC: H03K19/00 ,  H03K19/173 ,  G06F1/3234

CPC classification number: H03K19/0008 ,  G06F1/3243 ,  H02H3/06 ,  H02H3/087 ,  H03K19/1732

Abstract: A circuit includes a voltage source, a transistor, a load current sensor, a hardware latch and a logic circuit. The transistor is connected between the voltage source and a load. The sensor emits a fault signal when the load current exceeds a predetermined value. The hardware latch sets a latch signal when it receives the fault signal and maintains the latch signal until it receives a rearm signal. The logic circuit receives the latch signal from the hardware latch and also receives a software command for controlling turning on and off of the circuit. When the latch signal is not set, the logic circuit converts the software command to a control voltage applied at a gate of the transistor, turning on the transistor to allow power delivery to the load. A system includes a microcontroller providing software commands and rearm signals to a plurality of circuits.

公开(公告)号：US20190004812A1

公开(公告)日：2019-01-03

申请号：US16022524

申请日：2018-06-28

Applicant: Eta Compute, Inc.

Inventor： Ben Melton ,  Bryan Garnett Cope

IPC: G06F9/38 ,  H03K19/00 ,  G06F17/50 ,  H03K19/20 ,  G06F1/32

CPC classification number: G06F9/3871 ,  G06F1/3203 ,  G06F17/5059 ,  H03K19/0008 ,  H03K19/20

Abstract: There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.

公开(公告)号：US20180254778A1

公开(公告)日：2018-09-06

申请号：US15755021

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Van LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H03K19/00 ,  H03K19/094 ,  G06F1/32 ,  G06F17/50 ,  H01L27/02

CPC classification number: H03K19/0016 ,  G06F1/3203 ,  G06F17/5045 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/0008 ,  H03K19/0013 ,  H03K19/094

Abstract: A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

公开(公告)号：US10038444B2

公开(公告)日：2018-07-31

申请号：US15458692

申请日：2017-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Marco Rosselli ,  Daniele Mangano ,  Riccardo Condorelli

IPC: G06F7/38 ,  H03K19/00 ,  H03K19/177 ,  H03K19/173 ,  G06F15/78

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

公开(公告)号：US20180166432A1

公开(公告)日：2018-06-14

申请号：US15718275

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYO SIG WON ,  CHAN UK SHIN ,  KWANG OK JEONG ,  KWON CHIL KANG

IPC: H01L27/02 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/50 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L29/06 ,  H01L29/0649 ,  H01L2027/11881 ,  H03K3/0315 ,  H03K5/134 ,  H03K19/0008 ,  H03K2005/00195

Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.

公开(公告)号：US09998135B2

公开(公告)日：2018-06-12

申请号：US15673234

申请日：2017-08-09

Applicant: AnDAPT, Inc.

Inventor： Maheen Samad ,  Patrick J. Crotty ,  John Birkner ,  Herman Cheung ,  Kapil Shankar

IPC: H03M1/12 ,  H03M1/10 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03M1/1014 ,  H03K19/0008 ,  H03K19/017581 ,  H03M1/08 ,  H03M1/60

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

公开(公告)号：US09900006B2

公开(公告)日：2018-02-20

申请号：US15387132

申请日：2016-12-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H03K19/173 ,  H01L25/00 ,  H03K19/00 ,  H03K19/177 ,  G06F17/50

CPC classification number: H03K19/0008 ,  G06F17/5054 ,  H03K19/17756 ,  H03K19/1776

Abstract: A novel semiconductor device, a semiconductor device having a high computing performance, a semiconductor device capable of reducing power consumption, or a semiconductor device with a small area can be provided. The semiconductor device includes a CPU and a PLD, and an operation of the PLD is controlled by the CPU. Thus, the CPU executes processing which requires a complicated computation, a small amount of data processing, or the like by itself, and makes the PLD process a computation which requires a large amount of data processing, a computation which requires quick processing, or the like. In this way, the load of processing in the CPU is reduced and the frequency of access to a memory is reduced; accordingly, the operation speed and power efficiency of the semiconductor device is increased.

公开(公告)号：US20180048324A1

公开(公告)日：2018-02-15

申请号：US15673234

申请日：2017-08-09

Applicant: AnDAPT, Inc.

Inventor： Maheen Samad ,  Patrick J. Crotty ,  John Birkner ,  Herman Cheung ,  Kapil Shankar

IPC: H03M1/10 ,  H03K19/0175 ,  H03K19/00

CPC classification number: H03M1/1014 ,  H03K19/0008 ,  H03K19/017581 ,  H03M1/08 ,  H03M1/60

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

公开(公告)号：US09871519B2

公开(公告)日：2018-01-16

申请号：US15359573

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  Alexey Kostinsky

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US20170330873A1

公开(公告)日：2017-11-16

申请号：US15667672

申请日：2017-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA ,  Naoaki TSUTSUI ,  Atsuo ISOBE

IPC: H01L27/02 ,  H01L29/786 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  H01L23/532 ,  H03K19/00

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.