公开(公告)号：US20180323785A1

公开(公告)日：2018-11-08

申请号：US15875573

申请日：2018-01-19

申请人： Texas Instruments Incorporated

发明人： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC分类号： H03K19/00 ,  H03K19/0185 ,  G01R31/30 ,  G06F13/42

CPC分类号： H03K19/0008 ,  G01R31/3004 ,  G06F13/4282 ,  G06F2213/0016 ,  H03K19/0185

摘要： This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US20180286885A1

公开(公告)日：2018-10-04

申请号：US16000967

申请日：2018-06-06

申请人： Renesas Electronics Corporation

发明人： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC分类号： H01L27/118 ,  H03K3/03 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H03K17/16 ,  H03K3/037 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/00 ,  H01L29/78

CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/00346 ,  H01L2924/00

摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US09979393B2

公开(公告)日：2018-05-22

申请号：US15381477

申请日：2016-12-16

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： Hervé Fanet ,  Samer Houri ,  Gaël Pillonnet

IPC分类号： H03K19/00 ,  H03K19/185 ,  H03K19/02

CPC分类号： H03K19/0008 ,  H03K19/0013 ,  H03K19/0019 ,  H03K19/02 ,  H03K19/185 ,  H03K19/20

摘要： The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.

公开(公告)号：US09900007B2

公开(公告)日：2018-02-20

申请号：US15454225

申请日：2017-03-09

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Seiichi Yoneda ,  Tatsuji Nishijima

IPC分类号： H03K19/00 ,  H03K19/177 ,  H01L29/786 ,  H01L27/12

CPC分类号： H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K19/0008 ,  H03K19/17736 ,  H03K19/17744

摘要： An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

公开(公告)号：US09762243B2

公开(公告)日：2017-09-12

申请号：US14989052

申请日：2016-01-06

申请人： STMicroelectronics International N.V

发明人： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC分类号： H03K19/01 ,  H03K19/00 ,  H03K19/0175 ,  G06F1/32

CPC分类号： H03K19/017545 ,  G06F1/329 ,  H03K19/0008 ,  Y02D10/24 ,  Y10T307/406

摘要： An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction.

公开(公告)号：US09735778B1

公开(公告)日：2017-08-15

申请号：US14464588

申请日：2014-08-20

申请人： Altera Corporation

发明人： Jeffrey Schulz

IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/0008 ,  G06F1/3206 ,  G06F1/3243 ,  H03K19/003 ,  H03K19/17728 ,  H03K19/17744

摘要： Input-output (IO) circuitry for optimizing power management on an integrated circuit is disclosed. The IO circuitry includes monitoring circuitry and a multiplexer circuit that is controlled by the monitoring circuitry. The monitoring circuitry determines whether majority of the bits of an IO signal are transitioning from a first logical state to a second logical state. When a number of bit transitions of the IO signal exceeds a predetermined bit transition threshold, the monitoring circuitry may send a monitoring circuitry output to the multiplexer circuit to selectively couple an output signal to either the IO signal or an inverted IO signal. The IO circuitry further includes an additional multiplexer that receives the monitoring circuitry output and a clock signal. The additional multiplexer selects an additional output signal from the monitoring circuitry output and the clock signal based on a control signal that indicates a power-savings operation.

公开(公告)号：US20170213602A1

公开(公告)日：2017-07-27

申请号：US15285470

申请日：2016-10-04

申请人： Austemper Design Systems Inc.

发明人： Sanjay Pillay

IPC分类号： G11C29/12 ,  G11C29/54 ,  G06F17/50 ,  G11C29/52 ,  G11C11/412

CPC分类号： G11C29/12015 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2217/70 ,  G11C11/412 ,  G11C29/52 ,  G11C29/54 ,  H03K19/0008 ,  H03K19/21

摘要： Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design. Another such method involves using the design and a list of memories that need error correction code inserted automatically and limiting the impact to the clock cycle, by analyzing the timing to the inputs and from the outputs of the memories and inserting an in-line or a late timing wrapper, which includes the ECC insert during writes, and ECC check and correct during reads, identifying the registers that need to be shadowed and used in the delayed ECC correct cycle, identifying the clock gating required for various elements in the design to get the correct logic at the conclusion of the re-play cycle of ECC correction in case of late timing ECC correction.

公开(公告)号：US09704882B2

公开(公告)日：2017-07-11

申请号：US15199004

申请日：2016-06-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC分类号： H03K19/00 ,  H01L27/12 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/0185 ,  G11C7/04

CPC分类号： H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

摘要： A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170187380A1

公开(公告)日：2017-06-29

申请号：US15458692

申请日：2017-03-14

申请人： STMicroelectronics S.r.l.

发明人： Salvatore Marco Rosselli ,  Daniele Mangano ,  Riccardo Condorelli

IPC分类号： H03K19/00 ,  H03K19/173 ,  G06F15/78 ,  H03K19/177

CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

摘要： A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

公开(公告)号：US20170117901A1

公开(公告)日：2017-04-27

申请号：US15361411

申请日：2016-11-26

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas Carmean ,  Alexander Braun ,  Anna Y. Herr ,  Quentin P. Herr

IPC分类号： H03K19/195 ,  H03K19/20 ,  H03K3/037

CPC分类号： H03K19/195 ,  H03K3/037 ,  H03K3/38 ,  H03K19/0008 ,  H03K19/20

摘要： A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.