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    Programmable on-die termination timing in a multi-rank system
    3.
    发明授权
    Programmable on-die termination timing in a multi-rank system 有权

    公开(公告)号：US10141935B2

    公开(公告)日：2018-11-27

    申请号：US14865866

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Kuljit S Bains ,  Alexey Kostinsky ,  Nadav Bonen

    IPC分类号： G06F13/00 ,  G11C7/00 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  G06F3/06 ,  G06F13/16

    摘要： On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

    PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM
    6.
    发明申请
    PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM 审中-公开

    公开(公告)号：US20170093400A1

    公开(公告)日：2017-03-30

    申请号：US14865866

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

    IPC分类号： H03K19/0175 ,  G06F3/06 ,  G06F13/16

    CPC分类号： H03K19/017545 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1668

    摘要： On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

    INTERFERENCE TESTING
    7.
    发明申请
    INTERFERENCE TESTING 有权
    干扰测试

    公开(公告)号：US20150280781A1

    公开(公告)日：2015-10-01

    申请号：US14229460

    申请日：2014-03-28

    申请人： Intel Corporation

    发明人： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenien ,  James M. Shehadi

    IPC分类号： H04B3/46

    CPC分类号： H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

    摘要： In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

    摘要翻译： 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。

    Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals
    8.
    发明授权
    Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals 有权
    在不确定的初始条件下对指令/地址/控制/时钟延迟进行训练，并将旋转数据映射到命令/地址信号

    公开(公告)号：US09026725B2

    公开(公告)日：2015-05-05

    申请号：US13728581

    申请日：2012-12-27

    申请人： Intel Corporation

    发明人： Alexey Kostinsky ,  Zvika Greenfield ,  Christopher P. Mozak ,  Pavel Konev ,  Olga Fomenko

    IPC分类号： G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02

    CPC分类号： G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

    摘要： Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

    摘要翻译： 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。

    Programmable on-die termination timing in a multi-rank system
    9.
    发明授权
    Programmable on-die termination timing in a multi-rank system 有权

    公开(公告)号：US10680613B2

    公开(公告)日：2020-06-09

    申请号：US16146326

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

    IPC分类号： H03K19/0175 ,  G06F3/06 ,  G06F13/16

    摘要： On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.