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    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM
    3.
    发明申请
    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM 审中-公开
    用于动态调整电压参考以优化I / O系统的方法和装置

    公开(公告)号：US20160232962A1

    公开(公告)日：2016-08-11

    申请号：US15087963

    申请日：2016-03-31

    申请人： INTEL CORPORATION

    发明人： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

    IPC分类号： G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

    CPC分类号： G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

    摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

    摘要翻译： 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

    Transaction-level testing of memory I/O and memory device
    7.
    发明授权
    Transaction-level testing of memory I/O and memory device 有权
    内存I / O和内存设备的事务级别测试

    公开(公告)号：US08996934B2

    公开(公告)日：2015-03-31

    申请号：US13631961

    申请日：2012-09-29

    申请人： Intel Corporation

    发明人： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi

    IPC分类号： G11C29/00 ,  G11C29/08 ,  G11C29/56

    CPC分类号： G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    摘要： A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

    摘要翻译： 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎接收到一个命令，使其生成事务以实现内存测试。 该命令标识要实现的测试，并且测试引擎生成一个或多个存储器访问事务以在存储器设备上实现测试。 测试引擎将事务传递到内存控制器，可以使用其调度程序来调度命令。 因此，交易在存储设备中引起确定性行为，因为交易按照提供的方式执行，同时测试设备的实际操作。

    Memory subsystem I/O performance based on in-system empirical testing
    9.
    发明授权
    Memory subsystem I/O performance based on in-system empirical testing 有权

    公开(公告)号：US10446222B2

    公开(公告)日：2019-10-15

    申请号：US15372031

    申请日：2016-12-07

    申请人： Intel Corporation

    发明人： Theodore Z. Schoenborn ,  Christopher P. Mozak

    IPC分类号： G06F13/40 ,  G11C11/4093 ,  G11C29/56 ,  G11C29/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/04

    摘要： A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.