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    DELAY LINE WITH SHORT RECOVERY TIME
    3.
    发明申请
    DELAY LINE WITH SHORT RECOVERY TIME 审中-公开

    公开(公告)号：US20170346467A1

    公开(公告)日：2017-11-30

    申请号：US15419009

    申请日：2017-01-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Muhammad NUMMER

    IPC: H03K3/013 ,  H03K5/15

    CPC classification number: H03K5/15046 ,  H03K5/131 ,  H03K5/15 ,  H03K5/1508 ,  H03K2005/00234

    Abstract: A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

    METHOD FOR GENERATING A PLURALITY OF OSCILLATING SIGNALS WITH DIFFERENT PHASES AND ASSOCIATED CIRCUIT AND LOCAL OSCILLATOR
    4.
    发明申请
    METHOD FOR GENERATING A PLURALITY OF OSCILLATING SIGNALS WITH DIFFERENT PHASES AND ASSOCIATED CIRCUIT AND LOCAL OSCILLATOR 审中-公开
    用于产生具有不同相位和相关电路和本地振荡器的振荡信号的多项式的方法

    公开(公告)号：US20170012584A1

    公开(公告)日：2017-01-12

    申请号：US15098307

    申请日：2016-04-13

    Applicant: MEDIATEK INC.

    Inventor： Yueh-Ting Lee ,  Yao-Chi Wang ,  Sheng-Che Tseng

    IPC: H03B27/00 ,  H03K5/14 ,  H03K21/02 ,  H03L7/00

    CPC classification number: H03B27/00 ,  H03K5/14 ,  H03K21/02 ,  H03K2005/00234 ,  H03L7/00 ,  H03L7/0812

    Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

    Abstract translation: 用于产生具有不同相位的多个振荡信号的电路包括分频器，第一延迟链，第二延迟链和校准电路。 分频器被布置用于对第一输入信号和第二输入信号进行分频，以产生第一分频输入信号和第二分频输入信号。 第一延迟链被布置用于延迟第一分频输入信号，并且第二延迟链被布置用于延迟第二分频输入信号。 校准电路被配置为根据第一延迟链或第二延迟链内的信号来控制第一延迟链和第二延迟链的延迟量; 其中所述第一延迟链和所述第二延迟链内的部分延迟单元的输出信号用作具有不同相位的多个振荡信号。

    Delay cell and phase locked loop using the same
    7.
    发明授权
    Delay cell and phase locked loop using the same 有权

    公开(公告)号：US08072254B2

    公开(公告)日：2011-12-06

    申请号：US13102938

    申请日：2011-05-06

    Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

    Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

    IPC: H03H11/26

    CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

    Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

    Voltage controlled oscillator
    9.
    发明授权
    Voltage controlled oscillator 失效
    压控振荡器

    公开(公告)号：US07737795B2

    公开(公告)日：2010-06-15

    申请号：US11946932

    申请日：2007-11-29

    Applicant: Giri N. K. Rangan ,  Earl E. Swartzlander, Jr.

    Inventor： Giri N. K. Rangan ,  Earl E. Swartzlander, Jr.

    IPC: H03K3/03 ,  H03H11/26

    CPC classification number: H03K3/0322 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234

    Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.

    Abstract translation: 公开了一种基于环形振荡器的压控振荡器（VCO）。 VCO包括以环形配置彼此连接的一组延迟单元。 每个延迟单元包括源极耦合输入晶体管对，导流晶体管对和一对负载电阻。 源极耦合输入晶体管对接收一对差分电压输入。 连接到源极耦合输入晶体管对的负载电阻提供一对差分电压输出。 连接到源极耦合输入晶体管对的导流晶体管对接收一对差分偏置电压输入。 VCO的输出频率与差分偏置电压输入对的差分偏置电压成正比。

    Efficient delay elements
    10.
    发明授权
    Efficient delay elements 有权
    高效延时元件

    公开(公告)号：US07629825B1

    公开(公告)日：2009-12-08

    申请号：US11549427

    申请日：2006-10-13

    Applicant: Ryan Fung ,  Vaughn Betz

    Inventor： Ryan Fung ,  Vaughn Betz

    IPC: H03H11/26

    CPC classification number: H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    Abstract: Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    Abstract translation: 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

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