Invention Application
- Patent Title: DELAY LINE WITH SHORT RECOVERY TIME
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Application No.: US15419009Application Date: 2017-01-30
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Publication No.: US20170346467A1Publication Date: 2017-11-30
- Inventor: Muhammad NUMMER
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Main IPC: H03K3/013
- IPC: H03K3/013 ; H03K5/15

Abstract:
A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.
Public/Granted literature
- US10177751B2 Delay line with short recovery time Public/Granted day:2019-01-08
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