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    INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS
    1.
    发明申请
    INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20180212607A1

    公开(公告)日：2018-07-26

    申请号：US15700793

    申请日：2017-09-11

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Masato ODA

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/17792 ,  G11C13/0069 ,  H03K19/1735 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17732

    Abstract: An integrated circuit according to an embodiment includes: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row.

    Apparatus and method for correcting output signal of FPGA-based memory test device
    5.
    发明授权
    Apparatus and method for correcting output signal of FPGA-based memory test device 有权
    基于FPGA的存储器测试装置的输出信号校正装置和方法

    公开(公告)号：US09197212B2

    公开(公告)日：2015-11-24

    申请号：US14446482

    申请日：2014-07-30

    Applicant: UNITEST INC.

    Inventor： Ho Sang You

    IPC: H03K19/173 ,  G06F7/38 ,  H03K19/003 ,  H03K19/177

    CPC classification number: H03K19/00369 ,  H03K19/17792

    Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

    Abstract translation: 用于校正基于FPGA的存储器测试装置的输出信号的装置和方法包括用于输出具有不同相位的时钟信号的时钟发生器; 以及模式发生器，用于响应于从时钟发生器输入的时钟信号输出地址信号，数据信号和时钟信号，以及使用用于定时测量的触发器来校正每个输出信号的定时。 其中通过模式发生器的地址信号，数据信号和时钟信号用诸如FPGA的可编程逻辑来实现，从而在不使用外部延迟装置的情况下缩短校正时间，并且提高了 信号用于记忆测试，最终提高记忆测试仪的性能（精度）。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08283945B2

    公开(公告)日：2012-10-09

    申请号：US13255846

    申请日：2010-03-24

    Applicant: Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

    Inventor： Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

    IPC: G06F7/38 ,  H03K19/173 ,  H03K3/356

    CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

    Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

    Abstract translation: 作为常规可编程半导体器件的FPGA和MPLD具有差的成本性能，并未适当地考虑长信号线。 为了解决这个问题，在由多个MLUT组成的每个MLUT块中内置触发器，每个MLUT包括存储器和地址数据对。 相对于相邻MLUT之间的相邻线，引入了交替的相邻线，而在不相邻MLUT之间的互连的情况下，提供专用远距离线，此外，提供了环面互连网络。

    Power regulator circuitry for programmable logic device memory elements
    7.
    发明授权
    Power regulator circuitry for programmable logic device memory elements 有权
    用于可编程逻辑器件存储器元件的功率调节器电路

    公开(公告)号：US07859301B2

    公开(公告)日：2010-12-28

    申请号：US11799228

    申请日：2007-04-30

    Applicant: William Bradley Vest ,  Ping-Chen Liu ,  Thien Le

    Inventor： William Bradley Vest ,  Ping-Chen Liu ,  Thien Le

    IPC: H03K19/173 ,  G05F1/573 ,  G11C16/06

    CPC classification number: H03K19/0013 ,  G11C5/147 ,  H03K19/1776 ,  H03K19/17792

    Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

    Abstract translation: 提供了可编程逻辑器件集成电路上可编程存储器元件的功率调节器电路。 可编程存储器元件可各自包括由交叉耦合的反相器和地址晶体管形成的存储元件。 地址驱动器可用于向地址晶体管提供地址信号。 功率调节器电路可以包括地址电源电路，其向地址驱动器和存储元件电源电路产生时变地址电源电压，所述地址驱动器和存储元件电源电路向存储器中的交叉耦合的反相器提供时变存储元件电源电压 元素。 单位增益缓冲器可以用于将带隙电压基准的参考电压分配给电源电路。 电源电路可以使用分压器和p沟道金属氧化物半导体控制晶体管。

    Tuning programmable logic devices for low-power design implementation
    8.
    发明授权
    Tuning programmable logic devices for low-power design implementation 有权
    调整可编程逻辑器件，实现低功耗设计

    公开(公告)号：US07549139B1

    公开(公告)日：2009-06-16

    申请号：US10783216

    申请日：2004-02-20

    Applicant: Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    Inventor： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    IPC: G06F17/50 ,  H03K19/00

    CPC classification number: H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

    Abstract: A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

    Abstract translation: 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

    EFFICIENT DELAY ELEMENTS
    9.
    发明申请
    EFFICIENT DELAY ELEMENTS 有权
    有效的延迟元素

    公开(公告)号：US20090015308A1

    公开(公告)日：2009-01-15

    申请号：US12212314

    申请日：2008-09-17

    Applicant: Ryan FUNG ,  Vaughn Beth

    Inventor： Ryan FUNG ,  Vaughn Beth

    IPC: H03H11/26

    CPC classification number: H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    Abstract: Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    Abstract translation: 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS
    10.
    发明申请
    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 有权
    具有可编程逻辑器件集成电路的高电压电平的易失性存储器元件

    公开(公告)号：US20080266997A1

    公开(公告)日：2008-10-30

    申请号：US12169598

    申请日：2008-07-08

    Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    IPC: G11C5/14 ,  H03K19/173

    CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

    Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

    Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

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