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    Non-volatile memory array using single poly EEPROM in standard CMOS process
    3.
    发明授权
    Non-volatile memory array using single poly EEPROM in standard CMOS process 失效
    在标准CMOS工艺中使用单个多层EEPROM的非易失性存储器阵列

    公开(公告)号：US5959885A

    公开(公告)日：1999-09-28

    申请号：US828151

    申请日：1997-03-27

    Applicant: Kameswara K. Rao

    Inventor： Kameswara K. Rao

    IPC: G11C16/08 ,  G11C16/10 ,  G11C11/34

    CPC classification number: G11C16/08 ,  G11C16/10

    Abstract: Non-volatile storage elements are provided in an array on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit. The non-volatile storage elements are either EEPROM floating gate transistor cells, or other EEPROM cells using standard low voltage CMOS devices.

    Abstract translation: 在集成电路中的阵列中提供非易失性存储元件，其中非易失性存储元件是低电压CMOS器件，因此在制造意义上与集成电路上的其它类似晶体管兼容。 非易失性存储元件是EEPROM浮栅晶体管单元或使用标准低电压CMOS器件的其它EEPROM单元。

    Non-volatile storage for standard CMOS integrated circuits
    4.
    发明授权
    Non-volatile storage for standard CMOS integrated circuits 失效
    标准CMOS集成电路的非易失性存储

    公开(公告)号：US5835402A

    公开(公告)日：1998-11-10

    申请号：US825236

    申请日：1997-03-27

    Applicant: Kameswara K. Rao ,  Martin L. Voogel

    Inventor： Kameswara K. Rao ,  Martin L. Voogel

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C17/16 ,  G11C17/18 ,  G11C7/00

    CPC classification number: G11C17/18 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C17/16

    Abstract: Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.

    Abstract translation: 非易失性存储元件设置在集成电路上，其中非易失性存储元件是低电压CMOS器件，因此在制造意义上与集成电路上的其它类似晶体管兼容，从而不需要用于非集成电路的特殊类型的晶体管 非易失存储。 非易失性存储元件是通过破坏其栅极氧化物，EEPROM浮栅晶体管单元或其它EEPROM单元来编程的一次性可编程器件。

    Efficient in-system programming structure and method for non-volatile programmable logic devices
    5.
    发明授权
    Efficient in-system programming structure and method for non-volatile programmable logic devices 失效
    用于非易失性可编程逻辑器件的高效的在系统编程结构和方法

    公开(公告)号：US5734868A

    公开(公告)日：1998-03-31

    申请号：US512796

    申请日：1995-08-09

    Applicant: Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

    Inventor： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

    IPC: H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  H03K19/77

    CPC classification number: H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

    Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

    Abstract translation: 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

    Reset circuit for a programmable logic device
    6.
    发明授权
    Reset circuit for a programmable logic device 失效
    可编程逻辑器件的复位电路

    公开(公告)号：US5689516A

    公开(公告)日：1997-11-18

    申请号：US670916

    申请日：1996-06-26

    Applicant: Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

    Inventor： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

    IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/00

    CPC classification number: G01R31/318516 ,  G01R31/318558 ,  G06F11/2215

    Abstract: A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

    Abstract translation: 可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

    Disabling unused/inactive resources in an integrated circuit for static power reduction
    7.
    发明授权
    Disabling unused/inactive resources in an integrated circuit for static power reduction 有权
    禁用集成电路中的未使用/不活动资源以实现静态功耗降低

    公开(公告)号：US08099691B1

    公开(公告)日：2012-01-17

    申请号：US12491174

    申请日：2009-06-24

    Applicant: Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    Inventor： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC: G06F17/50

    CPC classification number: H03K19/17784

    Abstract: A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

    Abstract translation: 公开了一种操作集成电路（“IC”）的方法。 该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。 该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

    Tuning programmable logic devices for low-power design implementation
    8.
    发明授权
    Tuning programmable logic devices for low-power design implementation 有权
    调整可编程逻辑器件，实现低功耗设计

    公开(公告)号：US07549139B1

    公开(公告)日：2009-06-16

    申请号：US10783216

    申请日：2004-02-20

    Applicant: Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    Inventor： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    IPC: G06F17/50 ,  H03K19/00

    CPC classification number: H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

    Abstract: A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

    Abstract translation: 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

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