公开(公告)号：US08436656B2

公开(公告)日：2013-05-07

申请号：US13127473

申请日：2009-01-07

Applicant: Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

Inventor： Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

IPC: H03K19/0175

CPC classification number: H03K19/0008 ,  H03K19/017509 ,  H03K19/17704 ,  H03K19/17784

Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract translation: 一些实施例提供集成电路（'IC'），其包括以第一电压工作的至少第一和第二电路。 IC包括在第一和第二电路之间的直接连接，其包括用于以低于第一电压的第二电压将信号从第一电路传输到第二电路的第三电路。 第一和第二电路中的至少一个是用于可配置地执行操作的可配置电路。

公开(公告)号：US07936006B1

公开(公告)日：2011-05-03

申请号：US11244566

申请日：2005-10-06

Applicant: Yuhao Luo ,  Deepak Kumar Nayak ,  Daniel Gitlin

Inventor： Yuhao Luo ,  Deepak Kumar Nayak ,  Daniel Gitlin

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

Abstract: An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.

Abstract translation: MOS器件具有在器件的有源部分下方的嵌入式介质结构，例如源延伸或漏极延伸。 在替代实施例中，嵌入式介质结构位于MOS器件的沟道区域以及源极和漏极延伸部分之下。

公开(公告)号：US07772093B2

公开(公告)日：2010-08-10

申请号：US11977810

申请日：2007-10-26

Applicant: Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak Kumar Nayak ,  Daniel Gitlin

Inventor： Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak Kumar Nayak ,  Daniel Gitlin

IPC: H01L21/326 ,  H01L21/479

CPC classification number: H01L27/0251

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract translation: 公开了一种保护形成在集成电路的管芯上的晶体管的方法。 该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。 还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

公开(公告)号：US07294888B1

公开(公告)日：2007-11-13

申请号：US11240030

申请日：2005-09-30

Applicant: Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US06740936B1

公开(公告)日：2004-05-25

申请号：US10134086

申请日：2002-04-25

Applicant: Daniel Gitlin ,  James Karp ,  Jongheon Jeong ,  Jan L. de Jong

Inventor： Daniel Gitlin ,  James Karp ,  Jongheon Jeong ,  Jan L. de Jong

IPC: H01L2978

CPC classification number: H01L29/8605

Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Abstract translation: 形成在晶体管漏极和漏极接触之间的具有镇流电阻的晶体管由镇流电阻器的掩蔽区域形成，以增加电阻率，从而减少所需面积。 本发明实现了这一点，而不引入任何附加的处理或掩蔽步骤。 因此，本发明允许针对相同ESD要求降低IC管芯尺寸，或者允许针对给定裸片尺寸的更好的ESD保护。

公开(公告)号：US07839693B1

公开(公告)日：2010-11-23

申请号：US12683585

申请日：2010-01-07

Applicant: Sunhom Paak ,  Boon Y. Ang ,  Hsung J. Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Y. Ang ,  Hsung J. Im ,  Daniel Gitlin

IPC: G11C16/06

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US06621325B2

公开(公告)日：2003-09-16

申请号：US09956203

申请日：2001-09-18

Applicant: Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

Inventor： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

IPC: H03K301

CPC classification number: H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract translation: 用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。 用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。 在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。 在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

公开(公告)号：US5880620A

公开(公告)日：1999-03-09

申请号：US840582

申请日：1997-04-22

Applicant: Daniel Gitlin ,  Sheau-Suey Li ,  Martin L. Voogel ,  Tiemin Zhao

Inventor： Daniel Gitlin ,  Sheau-Suey Li ,  Martin L. Voogel ,  Tiemin Zhao

IPC: G11C5/14 ,  H03K17/06 ,  H03K3/01

CPC classification number: G11C5/146 ,  H03K17/063 ,  H03K2217/0018

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

Abstract translation: 通路电路包括通过晶体管和体偏置控制电路，用于偏置通过晶体管的主体以减小体效应。 体偏置控制电路包括一个或多个控制晶体管，其布置成当预定电压施加到传输晶体管的漏极和栅极时，选择性地将传输晶体管的衬底（主体）连接到传输晶体管的漏极或栅极。 结果，通过晶体管在导通状态下表现出减小的体效应。 在一个实施例中，体偏置控制电路包括第一控制晶体管，其具有连接到传输晶体管的栅极的漏极和栅极，连接到传输晶体管的漏极的栅极和源极。 体偏置控制电路还包括第二控制晶体管，其具有连接到第一控制晶体管的源极的漏极，连接到传输晶体管的主体的源极和连接到通过晶体管的漏极的栅极。 传输晶体管，第一控制晶体管和第二控制晶体管的主体电互连。 通过这种布置，只有当传输晶体管的栅极和漏极都处于高电压电平时，传输晶体管的主体被传输晶体管的栅极偏置“高”。

公开(公告)号：US5870327A

公开(公告)日：1999-02-09

申请号：US963532

申请日：1997-11-03

Applicant: Daniel Gitlin ,  Dennis L. Segers ,  Michael J. Hart

Inventor： Daniel Gitlin ,  Dennis L. Segers ,  Michael J. Hart

IPC: G11C7/20 ,  G11C17/00

CPC classification number: G11C7/20

Abstract: A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.

Abstract translation: 混合模式RAM / ROM单元包括易失性存储单元和耦合到单元的反熔丝。 在混合模式存储器单元的阵列中，寻址电路耦合到易失性存储器单元，并且编程电路耦合到反熔丝。 在反熔丝被编程之后，相关联的存储器单元从易失性存储器转换成非易失性存储器。 具体地说，在正常操作期间，向所有反熔丝提供标准电源电压。 因此，在断电或功率波动之后，编程的反熔丝确保其各自的易失性存储单元的后续配置。

公开(公告)号：US20110267103A1

公开(公告)日：2011-11-03

申请号：US13127473

申请日：2009-01-07

Applicant: Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

Inventor： Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

IPC: H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/017509 ,  H03K19/17704 ,  H03K19/17784

Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract translation: 一些实施例提供集成电路（'IC'），其包括以第一电压工作的至少第一和第二电路。 IC包括在第一和第二电路之间的直接连接，其包括用于以低于第一电压的第二电压将信号从第一电路传输到第二电路的第三电路。 第一和第二电路中的至少一个是用于可配置地执行操作的可配置电路。