公开(公告)号：US06774408B2

公开(公告)日：2004-08-10

申请号：US10183454

申请日：2002-06-28

申请人： Hideaki Ninomiya

发明人： Hideaki Ninomiya

IPC分类号： H01L2978

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7397

摘要： In a trench MOS gate structure of a semiconductor device where trenches (T) are located between an n-type base layer (1) and an n-type source layer (3), a p-type channel layer (12) is formed adjacent to side walls of the trenches, having an even concentration distribution along a depthwise dimension of the trenches. The p-type channel layer enables saturation current to decrease without a raise of ON-resistance of the device, and resultantly a durability against short-circuit can be enhanced. The n-type source layer formed adjacent to the side walls of the trench also further enhances the durability against short-circuit. Providing contacts of the emitter electrode (7) with the n-type source layer at the side walls of the trenches permits a miniaturization of the device and a reduction of the ON-resistance as well.

摘要翻译： 在沟槽（T）位于n型基极层（1）和n型源极层（3）之间的半导体器件的沟槽MOS栅极结构中，形成相邻的p型沟道层（12） 到沟槽的侧壁，沿着沟槽的深度尺寸具有均匀的浓度分布。 p型沟道层能够在不增加器件的导通电阻的情况下降低饱和电流，从而可以提高耐短路性。 与沟槽的侧壁相邻形成的n型源极层还进一步增强了对短路的耐久性。 在沟槽的侧壁处提供发射电极（7）与n型源极层的触点允许器件的小型化以及导通电阻的降低。

公开(公告)号：US06747326B2

公开(公告)日：2004-06-08

申请号：US10302965

申请日：2002-11-25

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L2978

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

摘要翻译： 一种用于调节Vt同时最小化低电压高速半导体器件的寄生电容的方法。 该方法使用阴影效应和倾斜冲击穿过垂直结构之间的预防植入物来提供分级植入物。 植入角度大于或等于S / H的反正切，其中S是水平距离，H是这种垂直结构的高度。

公开(公告)号：US06744103B2

公开(公告)日：2004-06-01

申请号：US10236685

申请日：2002-09-06

申请人： John P. Snyder

发明人： John P. Snyder

IPC分类号： H01L2978

CPC分类号： H01L21/823835 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/095 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.

摘要翻译： 公开了一种MOSFET器件及其制造方法。 本发明在MOSFET器件结构的上下文中利用用于源极和/或漏极接触制造的肖特基势垒接触，以消除对光晕/凹穴注入和浅源极/漏极扩展的需求以控制短沟道效应。 此外，本发明无条件地消除与MOSFET制造相关的寄生双极增益，降低了制造成本，加强了器件性能参数的控制，并且与现有技术相比提供了优异的器件特性。

公开(公告)号：US06680496B1

公开(公告)日：2004-01-20

申请号：US10191006

申请日：2002-07-08

申请人： Richard Hammond ,  Glyn Braithwaite

发明人： Richard Hammond ,  Glyn Braithwaite

IPC分类号： H01L2978

CPC分类号： H01L29/802

摘要： Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.

公开(公告)号：US06661061B1

公开(公告)日：2003-12-09

申请号：US09207437

申请日：1998-12-08

申请人： Mark I. Gardner ,  Fred N. Hause

发明人： Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L2978

CPC分类号： H01L27/0922 ,  H01L21/823857 ,  Y10S438/981

摘要： A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in an approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region 102 may alternatively be accomplished with rapid thermal anneal processing.

摘要翻译： 一种用于在集成电路内产生两个栅极氧化物厚度的半导体工艺，其中提供具有第一区域和第二区域的半导体衬底。 第一区域和第二区域相对于彼此横向移位。 然后将氮物质杂质分布引入半导体衬底的第一区域。 此后，在半导体衬底的上表面上生长栅极电介质层。 栅极电介质在半导体衬底的第一区域上具有第一厚度，并且在半导体衬底的第二区域上具有第二厚度。 第一厚度小于第二厚度。 在本发明的CMOS实施例中，半导体衬底的第一区域包括p型硅，而第二衬底区域包括n型硅。 优选地，将氮物质杂质分布引入半导体衬底的步骤是通过在含氮环境中热氧化第一衬底区域来实现的。 在目前优选的实施方案中，含氮环境包括大约比例为60:30:7:3的N2O，NH3，O2和HCl。 在替代实施方案中，含氮环境包括大约比例为90:7:3的N，O 2和HCl，N 2 O，O 2和HCl的比例大约为90:7:3。 可以通过快速热退火处理来实现将氮物质杂质引入到第一衬底区域102中。

公开(公告)号：US06635926B2

公开(公告)日：2003-10-21

申请号：US09908540

申请日：2001-07-20

申请人： Nobuki Miyakoshi ,  Toshiki Matsubara ,  Hideyuki Nakamura

发明人： Nobuki Miyakoshi ,  Toshiki Matsubara ,  Hideyuki Nakamura

IPC分类号： H01L2978

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7811

摘要： A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.

摘要翻译： 提供具有高耐受电压和低电阻的场效应晶体管。 环形沟道区域设置在形成在环中的源极区域内，并且沟道区域的内部被作为漏极区域。 耗尽层朝向漏极区域的内部延伸，导致高的耐受电压。 在该部分中，除了距通道区域的角部规定距离内的部分，设置低电阻导电层，从而导致高耐压。

公开(公告)号：US06635902B1

公开(公告)日：2003-10-21

申请号：US10153647

申请日：2002-05-24

申请人： Ming-Te Lin

发明人： Ming-Te Lin

IPC分类号： H01L2978

CPC分类号： H01L25/0753 ,  H01L2224/48137 ,  H01L2224/49107

摘要： A light emitting diode (LED) device includes a substrate having a major surface on which a number of LED chips are formed and arranged in a two-dimensional array. The LED chips have a p-type semiconductor and an n-type semiconductor. The n-type semiconductor of each LED chip is electrically connected to the p-type semiconductor of the adjacent LED chip, whereby the LED chips are connected in series. The p-type semiconductor of the starting LED chip and the n-type semiconductor of the ending LED chip are connected to conductors for electrical connection with an external power source. The arrangement of serially connected LED chips allows enhancement of the brightness of a single LED device when the size of the LED device is increased. The working voltage is also increased and the working current can be kept low. Interfacing equipment between the LED device and external power source can be simplified.

摘要翻译： 发光二极管（LED）装置包括具有主表面的基板，多个LED芯片形成在二维阵列上。 LED芯片具有p型半导体和n型半导体。 每个LED芯片的n型半导体电连接到相邻LED芯片的p型半导体，由此LED芯片串联连接。 起始LED芯片的p型半导体和结束LED芯片的n型半导体连接到与外部电源电连接的导体。 串行连接的LED芯片的布置允许当LED装置的尺寸增加时增强单个LED装置的亮度。 工作电压也增加，工作电流可以保持较低。 可以简化LED器件与外部电源之间的接口设备。

公开(公告)号：US06624468B2

公开(公告)日：2003-09-23

申请号：US10153617

申请日：2002-05-24

申请人： Masataka Takebuchi

发明人： Masataka Takebuchi

IPC分类号： H01L2978

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

摘要： In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

摘要翻译： 在其中非易失性存储元件和p沟道IGFET安装在单个衬底上的半导体器件中，将非易失性存储元件的隧道绝缘膜的氮化物原子密度设置为高于氮化物原子 P沟道IGFET的栅极绝缘膜的密度。 关于制造方法，当对非易失性存储元件的隧道绝缘膜进行硝化时，p沟道IGFET的栅极绝缘膜被厚缓冲氧化硅膜覆盖的区域。 由于在基板和缓冲氧化硅膜之间不形成氮化物膜，所以在形成栅极绝缘膜时能够可靠地除去缓冲氧化硅膜。

公开(公告)号：US06621122B2

公开(公告)日：2003-09-16

申请号：US10190152

申请日：2002-07-03

申请人： Zhijun Qu

发明人： Zhijun Qu

IPC分类号： H01L2978

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/41766 ,  H01L29/7802

摘要： A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

公开(公告)号：US06590267B1

公开(公告)日：2003-07-08

申请号：US09661997

申请日：2000-09-14

申请人： Scott H. Goodwin-Johansson ,  Gary E. McGuire

发明人： Scott H. Goodwin-Johansson ,  Gary E. McGuire

IPC分类号： H01L2978

CPC分类号： F16K99/0001 ,  B81B3/0021 ,  B81B2201/054 ,  B81B2203/0127 ,  B81B2203/04 ,  F15C5/00 ,  F16K99/0007 ,  F16K99/0028 ,  F16K99/0051 ,  F16K2099/0074 ,  F16K2099/008 ,  H01H2059/0081

摘要： A MEMS (Micro Electro Mechanical System) valve device driven by electrostatic forces is provided. This valve device can provide for fast actuation, large valve force and large displacements while utilizing minimal power. The MEMS valve device includes a substrate having an aperture formed therein, a substrate electrode, a moveable membrane that overlies the aperture and has an electrode element and a biasing element. Additionally, at least one resiliently compressible dielectric layer is provided to insure electrical isolation between the substrate electrode and electrode element of the moveable membrane. In operation, a voltage differential is established between the substrate electrode and the electrode element of the moveable membrane to move the membrane relative to the aperture to thereby controllably adjust the portion of the aperture that is covered by the membrane. Additional embodiments provide for the resiliently compressible dielectric layer to be formed on either or both the substrate electrode and the moveable membrane and provide for either or both the valve seat surface and the valve seal surface. In yet another embodiment the resiliently compressible dielectric layer(s) have a textured surface; either at the valve seat, the valve seal or at both surfaces. In another embodiment of the invention a pressure-relieving aperture is defined within the substrate and is positioned to underlie the moveable membrane. Alternatively, additional embodiments of the present invention provide for MEMS valve arrays driven by electrostatic forces. The MEMS valve array comprises a substrate having a plurality of apertures defined therein. A method for making the MEMS valve device is also provided.

摘要翻译： 提供了由静电力驱动的MEMS（微机电系统）阀装置。 该阀装置可以提供快速致动，大的阀力和大的位移，同时利用最小的功率。 MEMS阀装置包括其中形成有孔的基板，基板电极，覆盖在孔上并具有电极元件和偏置元件的可移动膜。 此外，提供至少一个可弹性压缩介电层以确保基板电极和可移动​​膜的电极元件之间的电隔离。 在操作中，在基板电极和可移动​​膜的电极元件之间建立电压差以使膜相对于孔移动，从而可控地调节由膜覆盖的孔的部分。 另外的实施例提供了可弹性压缩的介电层，其形成在基板电极和可移动​​膜之一或两者上，并为阀座表面和阀密封表面中的一个或两者提供。 在另一个实施例中，弹性可压缩介电层具有纹理表面; 无论是在阀座，阀门密封件还是在两个表面。 在本发明的另一个实施例中，压力释放孔限定在衬底内并且被定位成可移动膜的下面。 或者，本发明的另外的实施例提供了由静电力驱动的MEMS阀阵列。 MEMS阀阵列包括其中限定有多个孔的基板。 还提供了制造MEMS阀装置的方法。