公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363439A1

公开(公告)日：2024-10-31

申请号：US18770861

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US12131901B2

公开(公告)日：2024-10-29

申请号：US16921232

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0223 ,  H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. In addition, the second fin structure is higher than the first fin structure. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering a top surface of the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the top surface of the first fin structure is not flat.

公开(公告)号：US12125908B2

公开(公告)日：2024-10-22

申请号：US17751198

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chan ,  Meng-Yueh Liu ,  Wei-Ken Lin

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

公开(公告)号：US20240339544A1

公开(公告)日：2024-10-10

申请号：US18744952

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Jen Lai ,  Wei-Yuan Lu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/78684

Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

公开(公告)号：US12113119B2

公开(公告)日：2024-10-08

申请号：US17573852

申请日：2022-01-12

Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： Chung-Yi Chen

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/7848

Abstract: An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

公开(公告)号：US12113118B2

公开(公告)日：2024-10-08

申请号：US17815181

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

公开(公告)号：US12112989B2

公开(公告)日：2024-10-08

申请号：US17815085

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/823814 ,  H01L21/30604 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/7848 ,  H10B10/12

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US12107163B2

公开(公告)日：2024-10-01

申请号：US17406395

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

IPC: H01L21/265 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7847 ,  H01L29/04 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L21/823814 ,  H01L21/823821

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, forming a gate spacer on opposing sides of the sacrificial gate structure, forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface having a first roughness, forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness, and subjecting the amorphized region to an annealing process to recrystallize the amorphized region to a crystalline region, and the crystalline region comprising a dislocation.

公开(公告)号：US12094761B2

公开(公告)日：2024-09-17

申请号：US18342855

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/82 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.