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公开(公告)号：US20220285552A1
公开(公告)日：2022-09-08
申请号：US17751198
申请日：2022-05-23
Inventor： Chia-Ling Chan , Meng-Yueh Liu , Wei-Ken Lin
IPC: H01L29/78 , H01L29/66 , H01L29/06 , H01L21/311 , H01L21/3115 , H01L21/225 , H01L21/8238
Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.
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公开(公告)号：US10700197B2
公开(公告)日：2020-06-30
申请号：US15816259
申请日：2017-11-17
Inventor： Chia-Ling Chan , Meng-Yueh Liu , Wei-Ken Lin
IPC: H01L29/78 , H01L29/66 , H01L21/22 , H01L29/06 , H01L21/311 , H01L21/3115 , H01L21/225 , H01L21/8238
Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.
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公开(公告)号：US20190305125A1
公开(公告)日：2019-10-03
申请号：US16431352
申请日：2019-06-04
Inventor： Wei-Ken Lin , Chun Te Li , Chih-Peng Hsu
IPC: H01L29/78 , H01L21/321 , H01L21/02 , H01L29/66 , H01L21/8234
Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
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公开(公告)号：US20200321465A1
公开(公告)日：2020-10-08
申请号：US16908305
申请日：2020-06-22
Inventor： Chia-Ling Chan , Meng-Yueh Liu , Wei-Ken Lin
IPC: H01L29/78 , H01L29/66 , H01L29/06 , H01L21/311 , H01L21/3115 , H01L21/225 , H01L21/8238
Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.
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公开(公告)号：US10658252B2
公开(公告)日：2020-05-19
申请号：US16390828
申请日：2019-04-22
Inventor： Jia-Ming Lin , Wei-Ken Lin , Shiu-Ko JangJian , Chun-Che Lin
IPC: H01L21/66 , H01L21/311 , H01L21/8234 , H01L21/84 , H01L21/3115 , H01L21/762 , H01L29/78
Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
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公开(公告)号：US20190279863A1
公开(公告)日：2019-09-12
申请号：US16422574
申请日：2019-05-24
Inventor： Wan-Yi Kao , Chung-Chi Ko , Li Chun Te , Hsiang-Wei Lin , Te-En Cheng , Wei-Ken Lin , Guan-Yao Tu , Shu Ling Liao
IPC: H01L21/02 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L21/311
Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
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公开(公告)号：US20190067027A1
公开(公告)日：2019-02-28
申请号：US15801194
申请日：2017-11-01
Inventor： Yin Wang , Hung-Ju Chou , Jiun-Ming Kuo , Wei-Ken Lin , Chun Te Li
IPC: H01L21/3105 , H01L29/78 , H01L29/06 , H01L21/8238
Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.
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公开(公告)号：US20180053697A1
公开(公告)日：2018-02-22
申请号：US15782161
申请日：2017-10-12
Inventor： Jia-Ming Lin , Wei-Ken Lin , Shiu-Ko JangJian , Chun-Che Lin
IPC: H01L21/66 , H01L29/78 , H01L21/3115 , H01L21/762 , H01L21/311
CPC classification number: H01L22/26 , H01L21/31105 , H01L21/31155 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L22/12 , H01L29/7846 , H01L29/785
Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
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公开(公告)号：US11205597B2
公开(公告)日：2021-12-21
申请号：US16458437
申请日：2019-07-01
Inventor： Wei-Chun Tan , I-Hsieh Wong , Te-En Cheng , Yung-Hui Lin , Wei-Ken Lin , Wei-Yang Lee , Chih-Hung Nien
IPC: H01L21/311 , H01L29/16 , H01L27/092 , H01L29/06 , H01L21/306 , H01L21/8238 , H01L21/02 , H01L21/265 , H01L21/308 , H01L21/3115 , H01L21/3065 , H01L29/66 , H01L29/08 , H01L21/027 , H01L21/762 , H01L21/266 , H01L29/36
Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.
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公开(公告)号：US10950431B2
公开(公告)日：2021-03-16
申请号：US16422574
申请日：2019-05-24
Inventor： Wan-Yi Kao , Chung-Chi Ko , Li Chun Te , Hsiang-Wei Lin , Te-En Cheng , Wei-Ken Lin , Guan-Yao Tu , Shu Ling Liao
IPC: H01L21/02 , H01L29/66 , H01L21/311 , H01L21/8234 , H01L27/088 , H01L21/266 , H01L21/265 , H01L21/3065 , H01L21/3105 , H01L21/762 , H01L29/36
Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
