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公开(公告)号：US20240363351A1
公开(公告)日：2024-10-31
申请号：US18765720
申请日：2024-07-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Yi Lee , Cheng-Lung Hung , Chi On Chui
IPC: H01L21/28 , H01L21/02 , H01L21/285 , H01L21/3115 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/786
CPC classification number: H01L21/28088 , H01L21/0259 , H01L21/28185 , H01L21/28518 , H01L21/3115 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L21/823871 , H01L27/092 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/4908 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78618 , H01L29/78696 , H01L29/0673
Abstract: In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.
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公开(公告)号：US12132119B2
公开(公告)日：2024-10-29
申请号：US17489181
申请日：2021-09-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kihwan Kim , Sunguk Jang , Sujin Jung , Youngdae Cho
IPC: H01L29/786 , H01L21/02 , H01L29/06 , H01L29/161 , H01L29/167 , H01L29/417 , H01L29/423 , H01L29/66
CPC classification number: H01L29/78696 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0259 , H01L29/0665 , H01L29/167 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78618
Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.
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公开(公告)号：US20240355909A1
公开(公告)日：2024-10-24
申请号：US18760217
申请日：2024-07-01
Applicant: Micron Technology, Inc.
Inventor： Masihhur R. Laskar , Jeffery B. Hull , Hung-Wei Liu
CPC classification number: H01L29/66553 , H01L21/02164 , H01L21/02282 , H01L21/02345 , H01L29/66666 , H01L29/6684 , H01L29/7827 , H01L29/78391 , H10B51/30
Abstract: Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.
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公开(公告)号：US20240355901A1
公开(公告)日：2024-10-24
申请号：US18302177
申请日：2023-04-18
Inventor： Jung-Hung CHANG , Shih-Cheng CHEN , Chih-Hao WANG , Chia-Cheng TSAI , Kuo-Cheng CHIANG , Zhi-Chang LIN , Chien-Ning YAO , Tsung-Han CHUANG
IPC: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775
CPC classification number: H01L29/66439 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/775
Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.
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公开(公告)号：US12125897B2
公开(公告)日：2024-10-22
申请号：US18343322
申请日：2023-06-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Lun Chen , Chao-Hsien Huang , Li-Te Lin , Chun-Hsiung Lin
IPC: H01L29/66 , H01L21/8234 , H01L21/8238 , H01L29/51 , H01L29/78
CPC classification number: H01L29/6653 , H01L21/823468 , H01L21/823864 , H01L29/515 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785
Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
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公开(公告)号：US12119394B2
公开(公告)日：2024-10-15
申请号：US17843601
申请日：2022-06-17
Inventor： Shahaji B. More , Chien Lin , Cheng-Han Lee , Shih-Chieh Chang , Shu Kuan
IPC: H01L29/66 , H01L21/306 , H01L21/8234 , H01L29/10 , H01L29/161 , H01L29/423 , H01L29/78
CPC classification number: H01L29/66818 , H01L21/30604 , H01L21/823431 , H01L29/1054 , H01L29/161 , H01L29/42392 , H01L29/66553 , H01L29/6656 , H01L29/785
Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
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公开(公告)号：US12119389B2
公开(公告)日：2024-10-15
申请号：US18360854
申请日：2023-07-28
Inventor： Chun Hsiung Tsai , Kuo-Feng Yu , Yu-Ming Lin , Clement Hsingjen Wann
IPC: H01L29/66 , H01L21/02 , H01L21/265 , H01L29/08 , H01L21/266 , H01L21/3105 , H01L21/762
CPC classification number: H01L29/66545 , H01L21/02164 , H01L21/02332 , H01L21/26513 , H01L29/0847 , H01L29/66553 , H01L29/6659 , H01L29/66795 , H01L21/266 , H01L21/31053 , H01L21/76224 , H01L29/665
Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.
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公开(公告)号：US20240339542A1
公开(公告)日：2024-10-10
申请号：US18741987
申请日：2024-06-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Che-Lun Chang , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC: H01L29/786 , H01L21/02 , H01L21/285 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/78
CPC classification number: H01L29/78618 , H01L21/02532 , H01L21/02603 , H01L21/28518 , H01L23/5286 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78696
Abstract: Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
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公开(公告)号：US20240339511A1
公开(公告)日：2024-10-10
申请号：US18746288
申请日：2024-06-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuo-Cheng Chiang , Shi Ning Ju , Kuan-Lun Cheng , Chih-Hao Wang , Cheng-Chi Chuang
IPC: H01L29/417 , H01L23/522 , H01L23/528 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L29/41733 , H01L23/5226 , H01L23/5286 , H01L29/0653 , H01L29/401 , H01L29/42392 , H01L29/66553 , H01L29/6681 , H01L29/78696
Abstract: A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.
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公开(公告)号：US20240334671A1
公开(公告)日：2024-10-03
申请号：US18735797
申请日：2024-06-06
Inventor： Ta-Chun LIN , Kuo-Hua PAN
IPC: H10B10/00 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H10B10/125 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/308 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823864 , H01L21/823878 , H01L27/0922 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78618 , H01L29/78696
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.
