公开(公告)号：US20240363753A1

公开(公告)日：2024-10-31

申请号：US18766828

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Hsueh-Chang Sung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

公开(公告)号：US20240363704A1

公开(公告)日：2024-10-31

申请号：US18771503

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

公开(公告)号：US20240363495A1

公开(公告)日：2024-10-31

申请号：US18767848

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Cheng-Hung WANG ,  Tsung-Lin LEE ,  Shiuan-Jeng LIN ,  Chun-Ming LIN ,  Wen-Chih CHIANG

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20240363345A1

公开(公告)日：2024-10-31

申请号：US18441352

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok KANG ,  Raman GAIRE ,  Hsueh Chung CHEN ,  In Soo JUNG ,  Houssam LAZKANI ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/306

CPC classification number: H01L21/02645 ,  H01L21/02532 ,  H01L21/2003 ,  H01L21/306

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

公开(公告)号：US12125915B2

公开(公告)日：2024-10-22

申请号：US17581300

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.

公开(公告)号：US20240347610A1

公开(公告)日：2024-10-17

申请号：US18757013

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28556 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41766 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US12119404B2

公开(公告)日：2024-10-15

申请号：US18344057

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Han Wang ,  Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02603 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

公开(公告)号：US12119403B2

公开(公告)日：2024-10-15

申请号：US18355997

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Max Liu ,  Yen-Ming Peng ,  Wei-Shuo Ho

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02667 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

公开(公告)号：US12113071B2

公开(公告)日：2024-10-08

申请号：US17869827

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02658

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

公开(公告)号：US20240332016A1

公开(公告)日：2024-10-03

申请号：US18742250

申请日：2024-06-13

Applicant: ASM IP Holding B.V.

Inventor： Amir Kajbafvala ,  Peter Westrom ,  Joe Margetis ,  Xin Sun ,  Caleb Miskin ,  Yen Lin Leow ,  Yanfu Lu

IPC: H01L21/02 ,  C23C16/08 ,  C23C16/455 ,  C23C16/52 ,  C30B25/16 ,  C30B25/18 ,  C30B29/52

CPC classification number: H01L21/0262 ,  C23C16/08 ,  C23C16/45512 ,  C23C16/52 ,  C30B25/165 ,  C30B25/186 ,  C30B29/52 ,  H01L21/02532

Abstract: A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.