公开(公告)号：US12218226B2

公开(公告)日：2025-02-04

申请号：US17081365

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Lin ,  Pei-Hsun Wang ,  Chih-Hao Wang ,  Kuo-Cheng Ching ,  Jui-Chien Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

公开(公告)号：US20240387287A1

公开(公告)日：2024-11-21

申请号：US18788153

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Kuo-Cheng Ching ,  Chun-Hsiung Lin ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

公开(公告)号：US11776854B2

公开(公告)日：2023-10-03

申请号：US17827219

申请日：2022-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Chih-Hao Wang ,  Chih-Chao Chou

IPC: H01L29/06 ,  H01L29/08 ,  H01L31/0352 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.

公开(公告)号：US12119404B2

公开(公告)日：2024-10-15

申请号：US18344057

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Han Wang ,  Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02603 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

公开(公告)号：US20230411218A1

公开(公告)日：2023-12-21

申请号：US18362987

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Kuo-Cheng Ching ,  Chun-Hsiung Lin ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L21/324 ,  H01L21/02 ,  H01L29/161

CPC classification number: H01L21/823807 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/324

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

公开(公告)号：US11335776B2

公开(公告)日：2022-05-17

申请号：US16787306

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Yu Wang ,  Pei-Hsun Wang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088 ,  H01L21/3105

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

公开(公告)号：US20210020524A1

公开(公告)日：2021-01-21

申请号：US16515484

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Hsun Wang ,  Shih-Cheng Chen ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.

公开(公告)号：US11855178B2

公开(公告)日：2023-12-26

申请号：US17875125

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Hsiung Lin ,  Pei-Hsun Wang ,  Chih-Chao Chou ,  Chia-Hao Chang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/6653 ,  H01L21/0337 ,  H01L21/764 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

公开(公告)号：US11837506B2

公开(公告)日：2023-12-05

申请号：US17100942

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Kuo-Cheng Ching ,  Chun-Hsiung Lin ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L21/324 ,  H01L21/02 ,  H01L29/161

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

公开(公告)号：US20230187281A1

公开(公告)日：2023-06-15

申请号：US18167100

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lo-Heng Chang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Jung-Hung Chang ,  Pei-Hsun Wang

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/66636 ,  H01L21/30604 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/823437 ,  H01L27/0886 ,  H01L21/823481 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/823468 ,  H01L29/1037 ,  H01L21/823418

Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.