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    INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS
    2.
    发明申请
    INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS 有权

    公开(公告)号：US20250006474A1

    公开(公告)日：2025-01-02

    申请号：US18216432

    申请日：2023-06-29

    Applicant: Applied Materials, Inc.

    Inventor： Naomi YOSHIDA ,  Nobuyuki SASAKI ,  Yoichi SUZUKI ,  Tomoyuki TADA ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H01J37/32 ,  C23C16/02 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  H01L21/768

    Abstract: A cluster tool for forming an interconnection structure includes a pre-clean chamber, a selective chemical vapor deposition (CVD) chamber, a plasma-enhanced CVD (PECVD) chamber, one or more transfer chambers coupled to the pre-clean chamber, the selective CVD chamber, and the PECVD chamber, and configured to transfer the interconnection structure between the pre-clean chamber, the selective CVD chamber, and the PECVD chamber without breaking vacuum environment, and a controller configured to cause pre-cleaning of an exposed surface of a metal layer formed within a first dielectric layer of the interconnection structure in the pre-clean chamber, selective deposition of a cap layer on the pre-cleaned surface of the metal layer in the selective CVD chamber, and deposition of deposit a second dielectric layer on the cap layer and an exposed surface of the first dielectric layer in the PECVD chamber.

    CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE
    4.
    发明公开
    CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE 审中-公开

    公开(公告)号：US20240136229A1

    公开(公告)日：2024-04-25

    申请号：US18462242

    申请日：2023-09-06

    Applicant: Applied Materials, Inc.

    Inventor： Jody FRONHEISER ,  Sai Hooi YEONG ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN ,  Lequn LIU

    IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/15 ,  H01L29/423

    CPC classification number: H01L21/823412 ,  H01L21/02507 ,  H01L29/15 ,  H01L29/42392

    Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.

    CONTACT FORMATION PROCESS FOR CMOS DEVICES
    5.
    发明公开
    CONTACT FORMATION PROCESS FOR CMOS DEVICES 审中-公开

    公开(公告)号：US20230377997A1

    公开(公告)日：2023-11-23

    申请号：US18123783

    申请日：2023-03-20

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Balasubramanian PRANATHARTHIHARAN ,  Benjamin COLOMBEAU ,  Anchuan WANG

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L21/823871 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76895

    Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

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