公开(公告)号：US12125946B2

公开(公告)日：2024-10-22

申请号：US17664577

申请日：2022-05-23

申请人： Silanna UV Technologies Pte Ltd

发明人： Petar Atanackovic

IPC分类号： H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC分类号： H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

摘要： The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

公开(公告)号：US12119382B2

公开(公告)日：2024-10-15

申请号：US18181272

申请日：2023-03-09

申请人： GlobalWafers Co., Ltd.

发明人： Jia-Zhe Liu ,  Yen Lun Huang ,  Chih-Yuan Chuang ,  Che Ming Liu ,  Wen-Ching Hsu ,  Manhsuan Lin

IPC分类号： H01L29/205 ,  H01L21/02 ,  H01L29/20

CPC分类号： H01L29/205 ,  H01L21/02458 ,  H01L21/02505 ,  H01L29/2003 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0262

摘要： A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x≤1 and y≥0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

公开(公告)号：US12095006B2

公开(公告)日：2024-09-17

申请号：US17664569

申请日：2022-05-23

申请人： Silanna UV Technologies Pte Ltd

发明人： Petar Atanackovic

IPC分类号： H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC分类号： H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

摘要： The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

公开(公告)号：US12020926B2

公开(公告)日：2024-06-25

申请号：US17653305

申请日：2022-03-03

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L21/02507 ,  H01L21/0245 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7833

摘要： A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

公开(公告)号：US20240170612A1

公开(公告)日：2024-05-23

申请号：US18423986

申请日：2024-01-26

申请人： Silanna UV Technologies Pte Ltd

发明人： Petar Atanackovic

IPC分类号： H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC分类号： H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/7786 ,  H01L2223/6627

摘要： In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.

公开(公告)号：US11990518B2

公开(公告)日：2024-05-21

申请号：US17234731

申请日：2021-04-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

摘要： The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US11923194B2

公开(公告)日：2024-03-05

申请号：US17728369

申请日：2022-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/0245 ,  H01L21/02507 ,  H01L21/02587 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

公开(公告)号：US20240072205A1

公开(公告)日：2024-02-29

申请号：US18480323

申请日：2023-10-03

申请人： Silanna UV Technologies Pte Ltd

发明人： Petar Atanackovic

IPC分类号： H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC分类号： H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/7786 ,  H01L2223/6627

摘要： The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (NixMgyZn1-x-y)2GeO4 wherein 0≤x≤1 and 0≤y≤1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.

公开(公告)号：US11848357B2

公开(公告)日：2023-12-19

申请号：US17648687

申请日：2022-01-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC分类号： H01L29/15 ,  H01L21/02

CPC分类号： H01L29/155 ,  H01L21/02507 ,  H01L21/02532

摘要： Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of sections from a top to a bottom thereof, wherein the plurality of sections has a same chemical composition and at least two different strains. For example, in one embodiment, the plurality of sections has a same chemical composition of epitaxially grown silicon (Si) and has alternating strains between a tensile strain and a compressive strain. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20230290742A1

公开(公告)日：2023-09-14

申请号：US18189581

申请日：2023-03-24

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Zhibin Chen ,  Ruihong Luo

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L29/20 ,  H01L29/15 ,  C30B25/18 ,  C30B29/40 ,  C30B29/68

CPC分类号： H01L23/562 ,  C30B25/183 ,  C30B29/68 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0254 ,  H01L21/02458 ,  H01L21/02507 ,  H01L29/155 ,  H01L29/2003

摘要： A nitride epitaxial structure is provided, including: a substrate; a nucleation layer, formed on the substrate, where the nucleation layer is an aluminum nitride layer or a gallium nitride layer; a buffer layer, formed on the nucleation layer, including K stacked group-III nitride double-layer structures, K ≥ 3, each double-layer structure includes an upper layer and a lower layer that are stacked, a band gap difference of each double-layer structure is a difference between a band gap of a material of the upper layer and a band gap of a material of the lower layer, and band gap differences of the K double-layer structures generally present a gradient trend along a thickness direction of the buffer layer; and an epitaxial layer, formed on the buffer layer, where a material of the epitaxial layer includes group-III nitride. A semiconductor device is further provided, including the nitride epitaxial structure.