公开(公告)号：US20240363442A1

公开(公告)日：2024-10-31

申请号：US18770052

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823418 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US20240363336A1

公开(公告)日：2024-10-31

申请号：US18771426

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei Liou ,  Yu Lun Ke ,  Yi-Wei Chiu

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02164 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76877

Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.

公开(公告)号：US20240363332A1

公开(公告)日：2024-10-31

申请号：US18768570

申请日：2024-07-10

Applicant: Applied Materials, Inc.

Inventor： Xiaoquan Min ,  Kwangduk D. Lee

IPC: H01L21/02 ,  C23C16/26 ,  H10B41/27

CPC classification number: H01L21/02115 ,  C23C16/26 ,  H01L21/02274 ,  H01L21/0228 ,  H10B41/27

Abstract: Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition rate of greater than 200 nm/hr; and purging the processing chamber.

公开(公告)号：US20240355637A1

公开(公告)日：2024-10-24

申请号：US18476390

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： John Soo Kim ,  Gwan Ho Kim ,  Ji Yoon Kim ,  Heung Sik Park ,  Keun Hee Bai ,  Jong Min Baek ,  Do Haing Lee ,  Jong Sun Lee

IPC: H01L21/32 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/32 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/76831

Abstract: A for fabricating a semiconductor device comprises forming a mask layer on a substrate, the mask layer defining a through hole that exposes an upper surface of the substrate, the mask layer comprising a first mask layer and a second mask layer, wherein the second mask layer is between the substrate and the first mask layer, and wherein the second mask layer comprises carbon. The method includes forming a liner layer on side walls of the through hole inside the second mask layer.

公开(公告)号：US12125946B2

公开(公告)日：2024-10-22

申请号：US17664577

申请日：2022-05-23

Applicant: Silanna UV Technologies Pte Ltd

Inventor： Petar Atanackovic

IPC: H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC classification number: H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

Abstract: The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

公开(公告)号：US12125911B2

公开(公告)日：2024-10-22

申请号：US17818595

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3065 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US12119221B2

公开(公告)日：2024-10-15

申请号：US18125509

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Hanhong Chen ,  Philip A. Kraus ,  Joseph AuBuchon

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/34 ,  C23C16/45542 ,  H01L21/0217 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02274

Abstract: A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.

公开(公告)号：US20240339318A1

公开(公告)日：2024-10-10

申请号：US18595374

申请日：2024-03-04

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. HUNG ,  Theresa Kramer GUARINI ,  Johanes F. SWENBERG

IPC: H01L21/02 ,  C23C8/16 ,  C23C8/36 ,  C23C8/80 ,  C23C16/02 ,  C23C16/40 ,  C23C16/455 ,  C23C16/52 ,  C23C16/56 ,  C23C28/04

CPC classification number: H01L21/02332 ,  C23C8/16 ,  C23C8/36 ,  C23C8/80 ,  C23C16/0227 ,  C23C16/405 ,  C23C16/45527 ,  C23C16/52 ,  C23C16/56 ,  C23C28/042 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/0234

Abstract: A method of forming a semiconductor structure includes performing a first deposition process to deposit a first high-K dielectric layer on a surface of a substrate, performing an interface formation process to form an interfacial layer on the surface of the substrate, performing a second deposition process to deposit a second high-K dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the first high-K dielectric layer and the second high-K dielectric layer, and performing an anneal process to passivate chemical bonds in the first high-K dielectric layer and the second high-K dielectric layer.

公开(公告)号：US20240337013A1

公开(公告)日：2024-10-10

申请号：US18746869

申请日：2024-06-18

Applicant: FUJIFILM Corporation

Inventor： Atsushi Mizutani ,  Akihiro Hakamata ,  Koichi Sato

IPC: C23C16/04 ,  C23C16/06 ,  C23C16/56 ,  H01L21/02

CPC classification number: C23C16/04 ,  C23C16/06 ,  C23C16/56 ,  H01L21/0228 ,  H01L21/02664

Abstract: An object of the present invention is to provide a chemical liquid for manufacturing a semiconductor, which is capable of forming an ALD film in a region targeted for ALD film formation and suppressing the formation of an ALD film in a region not targeted for ALD film formation, in a case where an ALD treatment is carried out after bringing the chemical liquid into contact with a predetermined substrate to form a modified film. Another object of the present invention is to provide a manufacturing method of a modified substrate using the above-mentioned chemical liquid, a manufacturing method of a laminate, and a chemical liquid container.
The chemical liquid for manufacturing a semiconductor of the present invention is a chemical liquid for manufacturing a semiconductor including a compound A having a specific functional group, an organic solvent, and a specific metal atom, in which a content of the compound A is more than 10 ppm by mass with respect to a total mass of the chemical liquid, a total content of the specific metal atom is 1,000 ppt by mass or less with respect to the total mass of the chemical liquid, a mass ratio of the content of the compound A to the content of the specific metal atom is 104 to 109, and a content of water contained in the chemical liquid is 1% by mass or less.

公开(公告)号：US12110584B2

公开(公告)日：2024-10-08

申请号：US17361231

申请日：2021-06-28

Applicant: Applied Materials, Inc.

Inventor： Chandan Das ,  Susmit Singha Roy ,  Bhaskar Jyoti Bhuyan ,  John Sudijono ,  Abhijit Basu Mallick ,  Mark Saly

IPC: C23C16/30 ,  C23C16/04 ,  C23C16/06 ,  C23C16/448 ,  H01L21/02

CPC classification number: C23C16/305 ,  C23C16/04 ,  C23C16/06 ,  C23C16/4485 ,  H01L21/0228

Abstract: Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a precursor and a chalcogenide reactant to form the transition metal dichalcogenide film. The exposures can be sequential or simultaneous.