公开(公告)号：US20240266169A1

公开(公告)日：2024-08-08

申请号：US18568801

申请日：2022-06-10

申请人： JUSUNG ENGINEERING CO., LTD.

发明人： Chul Joo HWANG

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/0262 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02664 ,  H01L29/66522

摘要： Provided is a method for manufacturing a power semiconductor device, which includes forming an active layer on an SiC substrate. The forming of the active layer includes injecting a source gas onto the SiC substrate, performing primary purging of injecting a purge gas after stopping the injecting of the source gas, injecting a reactant gas after stopping the primary purging, and performing secondary purging of injecting the purging gas after stopping the injecting of the reactant gas. Thus, in accordance with exemplary embodiments, the active layer may be formed at a low temperature. Therefore, a substrate or a thin film formed on the substrate may be prevented from being damaged by high-temperature heat. In addition, power or a time required for heating the substrate to form the active layer may be saved, and an overall process time may be shortened.

公开(公告)号：US20240234134A1

公开(公告)日：2024-07-11

申请号：US18291196

申请日：2022-07-07

申请人： ams-OSRAM International GmbH

发明人： Viola Miran Kueller ,  Adrian Stefan Avramescu ,  Hans-Jürgen Lugauer ,  Marc Hoffman ,  Andreas Waag ,  Lukas Peters ,  Christoph Margenfeld

IPC分类号： H01L21/02

CPC分类号： H01L21/02389 ,  H01L21/02664

摘要： In an embodiment a method for producing a growth substrate includes providing a substrate with a main surface, arranging a layer sequence on the main surface of the substrate, wherein the layer sequence comprises at least one semiconductor layer comprising a III-V compound semiconductor material, and annealing the layer sequence on the substrate, wherein the layer sequence comprises at least one intermediate layer and/or wherein a cover layer is arranged on the layer sequence, wherein a temperature during annealing is at least 1400° C., wherein the intermediate layer comprises a material selected from the following group: carbides, nitrides, oxides, oxynitrides, wherein the nitrides are nitrides of silicon, titanium, tantalum, yttrium, hafnium, scandium, tungsten, or zirconium, and wherein the cover layer comprises one of the following materials: tungsten nitride, aluminum carbonitride, molybdenum, tungsten, titanium, tantalum, hafnium, aluminum, titanium tungsten, graphite, or a photoresist.

公开(公告)号：US20240213085A1

公开(公告)日：2024-06-27

申请号：US18488718

申请日：2023-10-17

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Ho Sung KIM ,  Daemyeong GEUM

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76251 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02587 ,  H01L21/02664

摘要： Disclosed is a large-area III-V semiconductor layer transferring method. The large-area III-V semiconductor layer transferring method includes: forming III-V semiconductor dies on a lower substrate; forming dielectric patterns on the III-V semiconductor dies and the lower substrate exposed between the III-V semiconductor dies; forming a lower III-V semiconductor layer on the dielectric patterns and the III-V semiconductor dies; forming a sacrificial layer on the lower III-V semiconductor layer; forming an upper III-V semiconductor layer on the sacrificial layer; bonding an upper substrate onto the III-V semiconductor layer; and removing the sacrificial layer.

公开(公告)号：US12012669B2

公开(公告)日：2024-06-18

申请号：US16941095

申请日：2020-07-28

申请人： FUJIAN JING' AN OPTOELECTRONICS CO., LTD.

发明人： Mingxin Chen ,  Xuewu Wang

IPC分类号： C30B29/30 ,  C30B33/02 ,  H01L21/02 ,  H03H9/145

CPC分类号： C30B29/30 ,  C30B33/02 ,  H01L21/02664 ,  H03H9/14502

摘要： A method for processing a wafer includes subjecting the wafer to a reduction treatment with heat and a reducing agent that has a melting point of lower than 600° C. The wafer is made of a material selected from the group consisting of lithium tantalate, lithium niobate, and a combination thereof. The wafer and the reducing agent are spaced apart from each other so that the reducing agent indirectly interacts with the wafer during the reduction treatment. Also disclosed is a processed wafer obtained by the method.

公开(公告)号：US11996446B2

公开(公告)日：2024-05-28

申请号：US17400097

申请日：2021-08-11

申请人： Massachusetts Institute of Technology ,  Nanyang Technological University

发明人： Ming Dao ,  Ju Li ,  Zhe Shi ,  Subra Suresh

IPC分类号： H01L29/10 ,  B81B7/00 ,  H01L21/02 ,  H10N30/88

CPC分类号： H01L29/1054 ,  B81B7/008 ,  H01L21/02664 ,  H10N30/886

摘要： Compositions and methods related to straining defect doped materials as well as their methods of use in electrical circuits are generally described.

公开(公告)号：US20240136358A1

公开(公告)日：2024-04-25

申请号：US18538009

申请日：2023-12-13

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei YAMAZAKI

IPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11929279B2

公开(公告)日：2024-03-12

申请号：US17152390

申请日：2021-01-19

申请人： SK hynix Inc.

发明人： Jin Woong Kim

IPC分类号： H01L21/02 ,  H01L21/762 ,  H10B12/00

CPC分类号： H01L21/76224 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02661 ,  H01L21/02664 ,  H10B12/34 ,  H01L21/76229

摘要： A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

公开(公告)号：US11830880B2

公开(公告)日：2023-11-28

申请号：US16691730

申请日：2019-11-22

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei Yamazaki

IPC分类号： H01L27/105 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/12 ,  G11C11/405 ,  G11C16/04 ,  H01L21/8258 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207 ,  H01L28/60 ,  H01L29/7833

摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US20230369487A1

公开(公告)日：2023-11-16

申请号：US18226166

申请日：2023-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  National Taiwan University

发明人： Fang-Liang LU ,  I-Hsieh Wong ,  Shih-Ya Lin ,  CheeWee Liu ,  Samuel C. Pan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/08 ,  H01L21/268 ,  H01L29/165 ,  H01L29/10 ,  H01L29/161 ,  H01L21/28 ,  H01L29/06

CPC分类号： H01L29/7848 ,  H01L29/665 ,  H01L21/02664 ,  H01L21/0245 ,  H01L21/324 ,  H01L29/0847 ,  H01L21/02532 ,  H01L21/268 ,  H01L29/165 ,  H01L21/02381 ,  H01L29/1033 ,  H01L29/161 ,  H01L21/28255 ,  H01L29/66651 ,  H01L21/02535 ,  H01L29/1054 ,  H01L21/02579 ,  H01L21/02576 ,  H01L29/0649

摘要： A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.

公开(公告)号：US11791157B2

公开(公告)日：2023-10-17

申请号：US17185191

申请日：2021-02-25

申请人： THE UNIVERSITY OF BRISTOL

发明人： Martin Hermann Hans Kuball ,  James Wayne Pomeroy ,  Michael John Uren ,  Oliver Aneurin Williams

IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L21/78

CPC分类号： H01L21/02502 ,  H01L21/02664 ,  H01L21/6835 ,  H01L21/7806

摘要： The invention provides a method 100 of manufacturing a precursor 105a for use in manufacturing a semiconductor-on-diamond substrate 110, the method comprising:



a) starting with a base substrate 112;
b) forming a sacrificial carrier layer 114 on the base substrate, the sacrificial carrier layer comprising a single-crystal semiconductor;
c) forming a single-crystal nucleation layer 116 on the sacrificial carrier layer, the single-crystal nucleation layer arranged to nucleate diamond growth; and
d) forming a device layer 118 on the single-crystal nucleation layer, the device layer comprising a single-crystal semiconductor layer or multiple single-crystal semiconductor layers.