公开(公告)号：US11980029B2

公开(公告)日：2024-05-07

申请号：US17883652

申请日：2022-08-09

Applicant: eMemory Technology Inc.

Inventor： Hsueh-Wei Chen

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B41/35 ,  H10B41/70

CPC classification number: H10B41/70 ,  G11C16/045 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B41/35

Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.

公开(公告)号：US20240120339A1

公开(公告)日：2024-04-11

申请号：US18537929

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US20230397447A1

公开(公告)日：2023-12-07

申请号：US18235995

申请日：2023-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20230371286A1

公开(公告)日：2023-11-16

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC classification number: H10B69/00 ,  H01L29/7869 ,  H01L27/0688 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US11737279B2

公开(公告)日：2023-08-22

申请号：US17835134

申请日：2022-06-08

Applicant: KIOXIA CORPORATION

Inventor： Go Oike

IPC: H01L27/11573 ,  H10B43/40 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B53/20 ,  H01L23/532

CPC classification number: H10B43/40 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0688 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B53/20 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53271

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

公开(公告)号：US12132090B2

公开(公告)日：2024-10-29

申请号：US18371814

申请日：2023-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Shinpei Matsuda ,  Shunpei Yamazaki

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/788 ,  H10B41/70

CPC classification number: H01L29/42324 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7883 ,  H10B41/70

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US20240322046A1

公开(公告)日：2024-09-26

申请号：US18675249

申请日：2024-05-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Satoshi TORIUMI ,  Takashi HAMADA ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Yuji ASANO ,  Ryunosuke HONDA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H10B41/70

CPC classification number: H01L29/7869 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/14645 ,  H01L27/14649 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78648 ,  H01L29/78696 ,  H10B41/70

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

公开(公告)号：US11963374B2

公开(公告)日：2024-04-16

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H10B99/00 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B99/00 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/7833 ,  H10B12/00

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20240120340A1

公开(公告)日：2024-04-11

申请号：US18538161

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11942553B2

公开(公告)日：2024-03-26

申请号：US17124692

申请日：2020-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Kyeong Jeong ,  Yun Heub Song ,  Chang Hwan Choi ,  Hyeon Joo Seul

IPC: H01L29/786 ,  H01L29/66 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/60 ,  H10B41/70 ,  H10B43/23 ,  H10B43/27 ,  H10B51/20 ,  H10B53/20 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66757 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/60 ,  H10B41/70 ,  H10B43/23 ,  H10B43/27 ,  H10B51/20 ,  H10B53/20 ,  H10B63/84 ,  H10B63/845

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.